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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 714c79e5921b
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Aug 17, 2017

  1. Revert "xilinx: work around Ultrascale DDR register default parameter… 

    … idiocy"

This reverts commit b0470e9.
    @sbourdeauducq
    sbourdeauducq committed Aug 17, 2017

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    lforst Luca Forstner
    SSH Key Fingerprint: ljpBJ7bYHpwPGV7Y7sJZM+cMS44wfy1fkQqwY/900Nw
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    5638093 View commit details

  2. xilinx: use correct DDR register on KU

    @sbourdeauducq
    sbourdeauducq committed Aug 17, 2017
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    714c79e View commit details
Showing with 2 additions and 4 deletions.
  1. +2 −4 migen/build/xilinx/common.py
6 changes: 2 additions & 4 deletions migen/build/xilinx/common.py
View file
Original file line number Diff line number Diff line change
@@ -186,7 +186,6 @@ def lower(dr):
class XilinxDDROutputImplKU(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRE1",
p_SRTYPE="ASYNC",
i_C=clk, i_SR=0,
i_D1=i1, i_D2=i2, o_Q=o,
)
@@ -195,13 +194,12 @@ def __init__(self, i1, i2, o, clk):
class XilinxDDROutputKU:
@staticmethod
def lower(dr):
return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk)
return XilinxDDROutputImplKU(dr.i1, dr.i2, dr.o, dr.clk)


class XilinxDDRInputImplKU(Module):
def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDRE1",
p_SRTYPE="ASYNC",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0,
i_d=i,
@@ -214,7 +212,7 @@ def __init__(self, i, o1, o2, clk):
class XilinxDDRInputKU:
@staticmethod
def lower(dr):
return XilinxDDRInputImplS7(dr.i, dr.o1, dr.o2, dr.clk)
return XilinxDDRInputImplKU(dr.i, dr.o1, dr.o2, dr.clk)


xilinx_ku_special_overrides = {