m-labs · Aug 17, 2017 · Aug 17, 2017 · Aug 17, 2017
Showing with 122 additions and 149 deletions.

+4 −3 misoc/cores/liteeth_mini/phy/__init__.py

+1 −1 misoc/cores/liteeth_mini/phy/gmii_mii.py

+80 −0 misoc/cores/liteeth_mini/phy/rgmii.py

+0 −144 misoc/cores/liteeth_mini/phy/s6rgmii.py

+37 −1 misoc/targets/sayma_amc.py
diff --git a/misoc/cores/liteeth_mini/phy/__init__.py b/misoc/cores/liteeth_mini/phy/__init__.py
@@ -1,20 +1,21 @@
 from misoc.cores.liteeth_mini.common import *
 
 
-def LiteEthPHY(clock_pads, pads, **kwargs):
+def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
     # Autodetect PHY
     if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
             from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
-            return LiteEthPHYGMIIMII(clock_pads, pads, **kwargs)
+            return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
         else:
             # This is a pure 1G PHY
             from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
             return LiteEthPHYGMII(clock_pads, pads, **kwargs)
     elif hasattr(pads, "rx_ctl"):
         # This is a 10/100/1G RGMII PHY
-        raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
+        from misoc.cores.liteeth_mini.phy.rgmii import LiteEthPHYRGMII
+        return LiteEthPHYRGMII(clock_pads, pads, **kwargs)
     elif len(pads.tx_data) == 4:
         # This is a MII PHY
         from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII

diff --git a/misoc/cores/liteeth_mini/phy/gmii_mii.py b/misoc/cores/liteeth_mini/phy/gmii_mii.py
@@ -160,7 +160,7 @@ def __init__(self, clk_freq):
 
 
 class LiteEthPHYGMIIMII(Module, AutoCSR):
-    def __init__(self, clock_pads, pads, clk_freq=None):
+    def __init__(self, clock_pads, pads, clk_freq):
         self.dw = 8
         # Note: we can use GMII CRG since it also handles tx clock pad used for MII
         self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)

diff --git a/misoc/cores/liteeth_mini/phy/rgmii.py b/misoc/cores/liteeth_mini/phy/rgmii.py
@@ -0,0 +1,80 @@
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import DDROutput, DDRInput
+
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+from misoc.cores.liteeth_mini.common import *
+
+
+class LiteEthPHYRGMIITX(Module):
+    def __init__(self, pads):
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
+
+        # # #
+
+        self.specials += DDROutput(sink.stb, sink.stb, pads.tx_ctl, ClockSignal("eth_tx"))
+        for i in range(4):
+            self.specials += DDROutput(sink.data[i], sink.data[4+i], pads.tx_data[i],
+                                       ClockSignal("eth_tx"))
+        self.comb += sink.ack.eq(1)
+
+
+class LiteEthPHYRGMIIRX(Module):
+    def __init__(self, pads):
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
+
+        # # #
+
+        rx_ctl = Signal()
+        rx_data = Signal(8)
+
+        q0 = Signal()
+        self.specials += DDRInput(pads.rx_ctl, q0, rx_ctl, ClockSignal("eth_rx"))
+        for i in range(4):
+            self.specials += DDRInput(pads.rx_data[i], rx_data[4+i], rx_data[i],
+                                      ClockSignal("eth_rx"))
+
+        rx_ctl_d = Signal()
+        self.sync += rx_ctl_d.eq(rx_ctl)
+        eop = Signal()
+        self.comb += eop.eq(~rx_ctl & rx_ctl_d)
+
+        self.sync += [
+            source.stb.eq(rx_ctl),
+            source.data.eq(rx_data)
+        ]
+        self.comb += source.eop.eq(eop)
+
+
+class LiteEthPHYRGMIICRG(Module, AutoCSR):
+    def __init__(self, clock_pads, pads):
+        self._reset = CSRStorage()
+
+        # # #
+
+        self.clock_domains.cd_eth_rx = ClockDomain()
+        self.clock_domains.cd_eth_tx = ClockDomain()
+
+        self.specials += [
+            Instance("BUFG", i_I=clock_pads.rx, o_O=self.cd_eth_rx.clk),
+            DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
+        ]
+        self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
+
+        reset = self._reset.storage
+        if hasattr(pads, "rst_n"):
+            self.comb += pads.rst_n.eq(~reset)
+        self.specials += [
+            AsyncResetSynchronizer(self.cd_eth_tx, reset),
+            AsyncResetSynchronizer(self.cd_eth_rx, reset),
+        ]
+
+
+class LiteEthPHYRGMII(Module, AutoCSR):
+    def __init__(self, clock_pads, pads):
+        self.dw = 8
+        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads)
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
+        self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/misoc/cores/liteeth_mini/phy/s6rgmii.py b/misoc/cores/liteeth_mini/phy/s6rgmii.py
diff --git a/misoc/targets/sayma_amc.py b/misoc/targets/sayma_amc.py
@@ -8,6 +8,8 @@
 
 from misoc.cores.sdram_settings import MT41J256M16
 from misoc.cores.sdram_phy import kusddrphy
+from misoc.cores.liteeth_mini.phy import LiteEthPHY
+from misoc.cores.liteeth_mini.mac import LiteEthMAC
 from misoc.integration.soc_sdram import *
 from misoc.integration.builder import *
 
@@ -85,14 +87,48 @@ def __init__(self, sdram="ddram_64", sdram_controller_type="minicon", **kwargs):
         self.register_sdram(self.ddrphy, sdram_controller_type,
                             sdram_module.geom_settings, sdram_module.timing_settings)
 
+class MiniSoC(BaseSoC):
+    mem_map = {
+        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+    }
+    mem_map.update(BaseSoC.mem_map)
+
+    def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
+        BaseSoC.__init__(self, *args, **kwargs)
+
+        self.csr_devices += ["ethphy", "ethmac"]
+        self.interrupt_devices.append("ethmac")
+
+        eth_clocks = self.platform.request("eth_clocks")
+        self.submodules.ethphy = LiteEthPHY(eth_clocks,
+                                            self.platform.request("eth"), clk_freq=self.clk_freq)
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone",
+                                            nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots)
+        ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
+        self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base,
+                               ethmac_len)
+
+        self.crg.cd_sys.clk.attr.add("keep")
+        self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
+        # period constraints are required here because of vivado
+        self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_false_path_constraints(
+            self.crg.cd_sys.clk,
+            self.ethphy.crg.cd_eth_tx.clk, eth_clocks.rx)
+
 
 def main():
     parser = argparse.ArgumentParser(description="MiSoC port to the Sayma AMC")
     builder_args(parser)
     soc_sdram_args(parser)
+    parser.add_argument("--with-ethernet", action="store_true",
+                        help="enable Ethernet support")
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_sdram_argdict(args))
+    cls = MiniSoC if args.with_ethernet else BaseSoC
+    soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()