xilinx: work around Ultrascale DDR register default parameter idiocy

m-labs · Aug 17, 2017 · b0470e9 · b0470e9
1 parent f7816e4
commit b0470e9
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py
@@ -186,6 +186,7 @@ def lower(dr):
 class XilinxDDROutputImplKU(Module):
     def __init__(self, i1, i2, o, clk):
         self.specials += Instance("ODDRE1",
+                p_SRTYPE="ASYNC",
                 i_C=clk, i_SR=0,
                 i_D1=i1, i_D2=i2, o_Q=o,
         )
@@ -200,6 +201,7 @@ def lower(dr):
 class XilinxDDRInputImplKU(Module):
     def __init__(self, i, o1, o2, clk):
         self.specials += Instance("IDDRE1",
+            p_SRTYPE="ASYNC",
             p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
             p_IS_C_INVERTED=0,
             i_d=i,