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base repository: timvideos/HDMI2USB-litex-firmware
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head repository: timvideos/HDMI2USB-litex-firmware
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  • 5 commits
  • 10 files changed
  • 1 contributor

Commits on Jul 21, 2017

  1. third_party: Ignore libuip.

    @mithro
    mithro committed Jul 21, 2017
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    22ddb52 View commit details

  2. Updating submodules. 

     * litedram changed from 3fe29dd to 47755e5
 * liteeth changed from f6d8ddb to c43fb26
 * litepcie changed from 5dd794f to 6a69b46
 * litesata changed from c3b784f to 1b09801
 * litescope changed from 2f625c5 to 8d87992
 * liteusb changed from c212f5e to 7a17876
 * litevideo changed from 26e2fb9 to c4a01c9
 * litex changed from b34f7439 to f25e46c4

Full submodule status
--
 cb0ee55074d1d50e8e976026d6de759dc5494624 edid-decode (heads/master)
 d2ab903f2845551db3bd134f0841532946c7e850 flash_proxies (heads/master)
 47755e5637e3e0839362d4912636cc696c8c719e litedram (heads/master)
 c43fb269a7585526bf39256b9d8090725084af43 liteeth (remotes/origin/HEAD)
 6a69b46d587f5a7a4d3345e1f258e0d997ce607b litepcie (remotes/origin/HEAD)
 1b09801f06f06224de68fdc9c0e7297948d59569 litesata (heads/master)
 8d87992b957ade252cdc9d48ae7f860739557979 litescope (heads/master)
 7a17876bc7f8943a2a0b500e4c1cb1e454c680b6 liteusb (heads/master)
 c4a01c99d0ce1e815be0dc6a5d14ded8b765e9d7 litevideo (heads/master)
 f25e46c428f8f74e9ae4beba5ed839c7042d94c8 litex (remotes/origin/HEAD)
    @mithro
    mithro committed Jul 21, 2017
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    398f0e4 View commit details

  3. Updating submodules. 

     * litevideo changed from c4a01c9 to f628a61

Full submodule status
--
 cb0ee55074d1d50e8e976026d6de759dc5494624 edid-decode (heads/master)
 d2ab903f2845551db3bd134f0841532946c7e850 flash_proxies (heads/master)
 47755e5637e3e0839362d4912636cc696c8c719e litedram (heads/master)
 c43fb269a7585526bf39256b9d8090725084af43 liteeth (remotes/origin/HEAD)
 6a69b46d587f5a7a4d3345e1f258e0d997ce607b litepcie (remotes/origin/HEAD)
 1b09801f06f06224de68fdc9c0e7297948d59569 litesata (heads/master)
 8d87992b957ade252cdc9d48ae7f860739557979 litescope (heads/master)
 7a17876bc7f8943a2a0b500e4c1cb1e454c680b6 liteusb (heads/master)
 f628a61cff0aa133c390323619ba86d3c1378eb6 litevideo (remotes/origin/HEAD)
 f25e46c428f8f74e9ae4beba5ed839c7042d94c8 litex (remotes/origin/HEAD)
    @mithro
    mithro committed Jul 21, 2017
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    35b2b5a View commit details

Commits on Jul 22, 2017

  1. travis: Skip the scope target for now.

    @mithro
    mithro committed Jul 22, 2017
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    bcedb07 View commit details

  2. Merge pull request #329 from mithro/litex-update 

    Update third_party modules.
    @mithro
    mithro authored Jul 22, 2017
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    64972e6 View commit details
Showing with 11 additions and 11 deletions.
  1. +2 −2 .travis.yml
  2. +1 −1 third_party/litedram
  3. +1 −1 third_party/liteeth
  4. +1 −1 third_party/litepcie
  5. +1 −1 third_party/litesata
  6. +1 −1 third_party/litescope
  7. +1 −1 third_party/liteusb
  8. +1 −1 third_party/litevideo
  9. +1 −1 third_party/litex
  10. +1 −1 third_party/merge-upstream.sh
4 changes: 2 additions & 2 deletions .travis.yml
View file
Original file line number Diff line number Diff line change
@@ -33,12 +33,12 @@ env:
# - PLATFORM=netv2
# - PLATFORM=nexys_video
# - PLATFORM=pipistrello
- CPU=lm32 PLATFORM=opsis SKIP_TARGETS="hdmi2usb\|video.*"
- CPU=lm32 PLATFORM=opsis SKIP_TARGETS="hdmi2usb\|video.*\|memtest"
- CPU=or1k PLATFORM=opsis TARGETS="base net"
- PLATFORM=opsis TARGET=video
- PLATFORM=opsis TARGET=hdmi2usb
# - PLATFORM=sim
- CPU=lm32 PLATFORM=mimasv2
- CPU=lm32 PLATFORM=mimasv2 TARGETS="base"
- CPU=or1k PLATFORM=mimasv2 TARGETS="base" # or1k and memtest don't fit on mimasv2

install:
2 changes: 1 addition & 1 deletion third_party/litedram
Submodule litedram updated 9 files
+13 −10 README
+7 −6 litedram/common.py
+1 −1 litedram/core/bankmachine.py
+86 −54 litedram/frontend/bist.py
+3 −3 litedram/frontend/crossbar.py
+5 −5 litedram/phy/dfi.py
+3 −0 litedram/phy/k7ddrphy.py
+27 −25 litedram/phy/kusddrphy.py
+0 −70 test/test_bitslip.py
2 changes: 1 addition & 1 deletion third_party/liteeth
Submodule liteeth updated 14 files
+1 −1 example_designs/targets/etherbone.py
+6 −10 example_designs/test/test_logic_analyzer.py
+5 −6 liteeth/core/arp.py
+1 −1 liteeth/core/icmp.py
+6 −6 liteeth/core/ip.py
+1 −1 liteeth/core/mac/gap.py
+3 −3 liteeth/core/mac/preamble.py
+37 −19 liteeth/core/udp.py
+52 −32 liteeth/frontend/etherbone.py
+3 −0 liteeth/phy/gmii.py
+8 −2 liteeth/phy/gmii_mii.py
+3 −0 liteeth/phy/mii.py
+2 −0 liteeth/phy/rmii.py
+1 −1 test/test_etherbone.py
2 changes: 1 addition & 1 deletion third_party/litepcie
Submodule litepcie updated 22 files
+7 −6 README
+4 −5 example_designs/targets/dma.py
+1 −1 litepcie/common.py
+12 −6 litepcie/core/crossbar.py
+1 −1 litepcie/core/msi.py
+3 −3 litepcie/core/tlp/controller.py
+12 −2 litepcie/core/tlp/depacketizer.py
+8 −3 litepcie/core/tlp/packetizer.py
+7 −21 litepcie/frontend/dma.py
+15 −12 litepcie/frontend/wishbone.py
+103 −79 litepcie/phy/s7pciephy.py
+29 −16 litepcie/phy/xilinx/7-series/artix7/pcie_core_top.v
+36 −21 litepcie/phy/xilinx/7-series/common/pcie.v
+30 −16 litepcie/phy/xilinx/7-series/common/pcie_gt_common.v
+30 −16 litepcie/phy/xilinx/7-series/common/pcie_gt_top.v
+30 −16 litepcie/phy/xilinx/7-series/common/pcie_pcie2_top.v
+30 −16 litepcie/phy/xilinx/7-series/common/pcie_phy.v
+30 −17 litepcie/phy/xilinx/7-series/common/pcie_pipe_wrapper.v
+29 −24 litepcie/phy/xilinx/7-series/common/pcie_qpll_wrapper.v
+30 −16 litepcie/phy/xilinx/7-series/common/pcie_support.v
+29 −16 litepcie/phy/xilinx/7-series/kintex7/pcie_core_top.v
+1 −1 test/test_dma.py
2 changes: 1 addition & 1 deletion third_party/litesata
Submodule litesata updated 2 files
+10 −9 README
+1 −3 example_designs/test/test_analyzer.py
2 changes: 1 addition & 1 deletion third_party/litescope
Submodule litescope updated 10 files
+8 −15 README
+3 −2 example_designs/make.py
+28 −3 example_designs/targets/simple.py
+14 −8 example_designs/test/test_analyzer.py
+7 −5 example_designs/test/test_regs.py
+41 −15 litescope/core.py
+48 −36 litescope/software/driver/analyzer.py
+1 −1 litescope/software/driver/io.py
+1 −1 litescope/software/dump/common.py
+20 −20 litescope/software/dump/sigrok.py
2 changes: 1 addition & 1 deletion third_party/liteusb
Submodule liteusb updated from c212f5 to 7a1787
2 changes: 1 addition & 1 deletion third_party/litevideo
Submodule litevideo updated from 26e2fb to f628a6
2 changes: 1 addition & 1 deletion third_party/litex
Submodule litex updated 78 files
+3 −0 .gitmodules
+5 −3 README
+5 −0 litex/boards/platforms/arty.py
+1 −1 litex/boards/platforms/nexys_video.py
+138 −0 litex/boards/platforms/versaecp55g.py
+7 −6 litex/boards/targets/arty.py
+30 −43 litex/boards/targets/kc705.py
+7 −10 litex/boards/targets/nexys_video.py
+9 −1 litex/boards/targets/sim.py
+15 −3 litex/build/lattice/diamond.py
+6 −2 litex/build/lattice/programmer.py
+11 −0 litex/build/sim/README
+42 −0 litex/build/sim/config.py
+40 −0 litex/build/sim/core/Makefile
+14 −0 litex/build/sim/core/error.h
+366 −0 litex/build/sim/core/libdylib.c
+118 −0 litex/build/sim/core/libdylib.h
+159 −0 litex/build/sim/core/modules.c
+40 −0 litex/build/sim/core/modules.h
+14 −0 litex/build/sim/core/modules/Makefile
+5 −0 litex/build/sim/core/modules/clocker/Makefile
+109 −0 litex/build/sim/core/modules/clocker/clocker.c
+17 −0 litex/build/sim/core/modules/ethernet/Makefile
+258 −0 litex/build/sim/core/modules/ethernet/ethernet.c
+1 −0 litex/build/sim/core/modules/ethernet/tapcfg
+9 −0 litex/build/sim/core/modules/rules.mak
+5 −0 litex/build/sim/core/modules/serial2console/Makefile
+183 −0 litex/build/sim/core/modules/serial2console/serial2console.c
+5 −0 litex/build/sim/core/modules/serial2tcp/Makefile
+258 −0 litex/build/sim/core/modules/serial2tcp/serial2tcp.c
+5 −0 litex/build/sim/core/modules/variables.mak
+80 −0 litex/build/sim/core/pads.c
+28 −0 litex/build/sim/core/pads.h
+339 −0 litex/build/sim/core/parse.c
+243 −0 litex/build/sim/core/sim.c
+804 −0 litex/build/sim/core/tinydir.h
+40 −0 litex/build/sim/core/veril.cpp
+16 −0 litex/build/sim/core/veril.h
+0 −492 litex/build/sim/dut_tb.cpp
+20 −0 litex/build/sim/platform.py
+102 −104 litex/build/sim/verilator.py
+10 −7 litex/build/xilinx/common.py
+2 −0 litex/build/xilinx/ise.py
+25 −25 litex/build/xilinx/programmer.py
+33 −4 litex/build/xilinx/vivado.py
+3 −1 litex/gen/fhdl/decorators.py
+9 −5 litex/gen/fhdl/specials.py
+24 −2 litex/gen/fhdl/structure.py
+3 −2 litex/gen/fhdl/tools.py
+14 −6 litex/gen/fhdl/verilog.py
+18 −15 litex/gen/genlib/cdc.py
+1 −0 litex/gen/genlib/fifo.py
+5 −2 litex/gen/genlib/record.py
+4 −4 litex/gen/sim/core.py
+1 −1 litex/gen/util/misc.py
+27 −0 litex/soc/cores/dna.py
+67 −0 litex/soc/cores/frequency_meter.py
+1 −1 litex/soc/cores/identifier.py
+44 −0 litex/soc/cores/uart.py
+64 −0 litex/soc/cores/xadc.py
+10 −14 litex/soc/integration/builder.py
+4 −3 litex/soc/integration/cpu_interface.py
+6 −3 litex/soc/integration/soc_core.py
+35 −9 litex/soc/interconnect/stream.py
+5 −3 litex/soc/interconnect/stream_packet.py
+6 −6 litex/soc/interconnect/wishbonebridge.py
+1 −1 litex/soc/software/libbase/id.c
+2 −0 litex/soc/tools/remote/__init__.py
+5 −5 litex/soc/tools/remote/comm_pcie.py
+3 −5 litex/soc/tools/remote/comm_udp.py
+4 −8 litex/soc/tools/remote/etherbone.py
+42 −19 litex/soc/tools/remote/litex_server.py
+1 −0 setup.py
+0 −0 test/__init__.py
+69 −0 test/test_bitslip.py
+106 −0 test/test_code_8b10b.py
+43 −0 test/test_gearbox.py
+44 −0 test/test_targets.py
2 changes: 1 addition & 1 deletion third_party/merge-upstream.sh
View file
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@

set -e

TARGETS=${@-$(find * -maxdepth 0 -type d | grep -v micropython | grep -v qemu)}
TARGETS=${@-$(find * -maxdepth 0 -type d | grep -v micropython | grep -v qemu | grep -v libuip)}

COMMIT_MSG=$(tempfile) || exit
trap "rm -f -- '$COMMIT_MSG'" EXIT