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Fixed more issues with GreenPAK counter sim models
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azonenberg committed Aug 15, 2017
1 parent 3c39135 commit e0e68f0
Showing 1 changed file with 23 additions and 19 deletions.
42 changes: 23 additions & 19 deletions techlibs/greenpak4/cells_sim_digital.v
Original file line number Diff line number Diff line change
@@ -58,23 +58,25 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);

"RISING": begin
always @(posedge CLK, posedge RST) begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;

if(RST)
count <= 0;
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end

"FALLING": begin
always @(posedge CLK, negedge RST) begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;

if(!RST)
count <= 0;
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end

@@ -88,7 +90,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
"LEVEL": begin
always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
count <= 0;

else begin
count <= count - 1'd1;
@@ -422,23 +424,25 @@ module GP_COUNT8(

"RISING": begin
always @(posedge CLK, posedge RST) begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;

if(RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end

"FALLING": begin
always @(posedge CLK, negedge RST) begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;

if(!RST)
count <= 0;
else begin
count <= count - 1'd1;
if(count == 0)
count <= COUNT_TO;
end
end
end

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