Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: azonenberg/yosys
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: e0e68f0c30d8
Choose a base ref
...
head repository: azonenberg/yosys
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: e3946e812cc2
Choose a head ref
  • 14 commits
  • 3 files changed
  • 2 contributors

Commits on Aug 14, 2017

  1. Copy the full SHA
    cca3cb5 View commit details
  2. Copy the full SHA
    66aac06 View commit details
  3. Copy the full SHA
    3dd7f42 View commit details
  4. Copy the full SHA
    2877d5e View commit details
  5. Copy the full SHA
    1bb150c View commit details
  6. Copy the full SHA
    1a6a23f View commit details
  7. Copy the full SHA
    d5e5bba View commit details
  8. Copy the full SHA
    bd2ac68 View commit details
  9. Copy the full SHA
    0ee27d0 View commit details
  10. Copy the full SHA
    15e41d6 View commit details

Commits on Aug 15, 2017

  1. Copy the full SHA
    9fe6bc4 View commit details
  2. Copy the full SHA
    88983f5 View commit details
  3. Copy the full SHA
    e991836 View commit details
  4. Merge https://github.com/cliffordwolf/yosys

    Conflicts:
    	passes/opt/Makefile.inc
    azonenberg committed Aug 15, 2017
    Copy the full SHA
    e3946e8 View commit details
Showing with 189 additions and 1 deletion.
  1. +1 −1 passes/opt/Makefile.inc
  2. +187 −0 passes/opt/rmports.cc
  3. +1 −0 passes/techmap/Makefile.inc
2 changes: 1 addition & 1 deletion passes/opt/Makefile.inc
Original file line number Diff line number Diff line change
@@ -6,7 +6,7 @@ OBJS += passes/opt/opt_reduce.o
OBJS += passes/opt/opt_rmdff.o
OBJS += passes/opt/opt_clean.o
OBJS += passes/opt/opt_expr.o
OBJS += passes/opt/opt_rmports.o
OBJS += passes/opt/rmports.o

ifneq ($(SMALL),1)
OBJS += passes/opt/share.o
187 changes: 187 additions & 0 deletions passes/opt/rmports.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,187 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/

#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/log.h"
#include <stdlib.h>
#include <stdio.h>

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct RmportsPassPass : public Pass {
RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" rmports [selection]\n");
log("\n");
log("This pass identifies ports in the selected modules which are not used or\n");
log("driven and removes them.\n");
log("\n");
}

virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");

size_t argidx = 1;
extra_args(args, argidx, design);

// The set of ports we removed
dict<IdString, pool<IdString>> removed_ports;

// Find all of the unused ports, and remove them from that module
auto modules = design->selected_modules();
for(auto mod : modules)
ScanModule(mod, removed_ports);

// Remove the unused ports from all instances of those modules
for(auto mod : modules)
CleanupModule(mod, removed_ports);
}

void CleanupModule(Module *module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Removing now-unused cell ports in module %s\n", module->name.c_str());

auto cells = module->cells();
for(auto cell : cells)
{
if(removed_ports.find(cell->type) == removed_ports.end())
{
// log(" Not touching instance \"%s\" because we didn't remove any ports from module \"%s\"\n",
// cell->name.c_str(), cell->type.c_str());
continue;
}

auto ports_to_remove = removed_ports[cell->type];
for(auto p : ports_to_remove)
{
log(" Removing port \"%s\" from instance \"%s\"\n",
p.c_str(), cell->type.c_str());
cell->unsetPort(p);
}
}
}

void ScanModule(Module* module, dict<IdString, pool<IdString>> &removed_ports)
{
log("Finding unconnected ports in module %s\n", module->name.c_str());

pool<IdString> used_ports;

// See what wires are used.
// Start by checking connections between named wires
auto &conns = module->connections();
for(auto sigsig : conns)
{
auto s1 = sigsig.first;
auto s2 = sigsig.second;

int len1 = s1.size();
int len2 = s2.size();
int len = len1;
if(len2 < len1)
len = len2;

for(int i=0; i<len; i++)
{
auto w1 = s1[i].wire;
auto w2 = s2[i].wire;
if( (w1 == NULL) || (w2 == NULL) )
continue;

//log(" conn %s, %s\n", w1->name.c_str(), w2->name.c_str());

if( (w1->port_input || w1->port_output) && (used_ports.find(w1->name) == used_ports.end()) )
used_ports.insert(w1->name);

if( (w2->port_input || w2->port_output) && (used_ports.find(w2->name) == used_ports.end()) )
used_ports.insert(w2->name);
}
}

// Then check connections to cells
auto cells = module->cells();
for(auto cell : cells)
{
auto &cconns = cell->connections();
for(auto conn : cconns)
{
for(int i=0; i<conn.second.size(); i++)
{
auto sig = conn.second[i].wire;
if(sig == NULL)
continue;

// log(" sig %s\n", sig->name.c_str());
if( (sig->port_input || sig->port_output) && (used_ports.find(sig->name) == used_ports.end()) )
used_ports.insert(sig->name);
}
}
}

// Now that we know what IS used, get rid of anything that isn't in that list
pool<IdString> unused_ports;
for(auto port : module->ports)
{
if(used_ports.find(port) != used_ports.end())
continue;
unused_ports.insert(port);
}

// Print the ports out as we go through them
for(auto port : unused_ports)
{
log(" removing unused port %s\n", port.c_str());
removed_ports[module->name].insert(port);

// Remove from ports list
for(size_t i=0; i<module->ports.size(); i++)
{
if(module->ports[i] == port)
{
module->ports.erase(module->ports.begin() + i);
break;
}
}

// Mark the wire as no longer a port
auto wire = module->wire(port);
wire->port_input = false;
wire->port_output = false;
wire->port_id = 0;
}
log("Removed %zu unused ports.\n", unused_ports.size());

// Re-number all of the wires that DO have ports still on them
for(size_t i=0; i<module->ports.size(); i++)
{
auto port = module->ports[i];
auto wire = module->wire(port);
wire->port_id = i+1;
}
}

} RmportsPassPass;

PRIVATE_NAMESPACE_END
1 change: 1 addition & 0 deletions passes/techmap/Makefile.inc
Original file line number Diff line number Diff line change
@@ -24,6 +24,7 @@ OBJS += passes/techmap/recover_adder_core.o
OBJS += passes/techmap/recover_reduce.o
OBJS += passes/techmap/recover_reduce_core.o
OBJS += passes/techmap/recover_tff.o
OBJS += passes/techmap/recover_tff_counters.o
$(eval $(call add_share_file,share/untechmap,passes/techmap/tff_untechmap.v))
OBJS += passes/techmap/alumacc.o
OBJS += passes/techmap/dff2dffe.o