m-labs · Aug 16, 2017 · Aug 16, 2017
Showing with 3 additions and 5 deletions.

+2 −2 misoc/cores/liteeth_mini/phy/__init__.py

+1 −1 misoc/cores/liteeth_mini/phy/gmii_mii.py

+0 −2 misoc/targets/kc705.py
diff --git a/misoc/cores/liteeth_mini/phy/__init__.py b/misoc/cores/liteeth_mini/phy/__init__.py
@@ -1,13 +1,13 @@
 from misoc.cores.liteeth_mini.common import *
 
 
-def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
+def LiteEthPHY(clock_pads, pads, **kwargs):
     # Autodetect PHY
     if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
             from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
-            return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
+            return LiteEthPHYGMIIMII(clock_pads, pads, **kwargs)
         else:
             # This is a pure 1G PHY
             from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII

diff --git a/misoc/cores/liteeth_mini/phy/gmii_mii.py b/misoc/cores/liteeth_mini/phy/gmii_mii.py
@@ -160,7 +160,7 @@ def __init__(self, clk_freq):
 
 
 class LiteEthPHYGMIIMII(Module, AutoCSR):
-    def __init__(self, clock_pads, pads, clk_freq):
+    def __init__(self, clock_pads, pads, clk_freq=None):
         self.dw = 8
         # Note: we can use GMII CRG since it also handles tx clock pad used for MII
         self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)

diff --git a/misoc/targets/kc705.py b/misoc/targets/kc705.py
@@ -73,8 +73,6 @@ def __init__(self, platform):
 
 
 class BaseSoC(SoCSDRAM):
-    default_platform = "kc705"
-
     def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
         platform = kc705.Platform(toolchain=toolchain)
         SoCSDRAM.__init__(self, platform,