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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 47637ed610d2
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Aug 16, 2017

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    514da94 View commit details
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    47637ed View commit details
Showing with 3 additions and 5 deletions.
  1. +2 −2 misoc/cores/liteeth_mini/phy/__init__.py
  2. +1 −1 misoc/cores/liteeth_mini/phy/gmii_mii.py
  3. +0 −2 misoc/targets/kc705.py
4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/phy/__init__.py
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
from misoc.cores.liteeth_mini.common import *


def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
def LiteEthPHY(clock_pads, pads, **kwargs):
# Autodetect PHY
if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
if hasattr(clock_pads, "tx"):
# This is a 10/100/1G PHY
from misoc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
return LiteEthPHYGMIIMII(clock_pads, pads, **kwargs)
else:
# This is a pure 1G PHY
from misoc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
2 changes: 1 addition & 1 deletion misoc/cores/liteeth_mini/phy/gmii_mii.py
Original file line number Diff line number Diff line change
@@ -160,7 +160,7 @@ def __init__(self, clk_freq):


class LiteEthPHYGMIIMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, clk_freq):
def __init__(self, clock_pads, pads, clk_freq=None):
self.dw = 8
# Note: we can use GMII CRG since it also handles tx clock pad used for MII
self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
2 changes: 0 additions & 2 deletions misoc/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -73,8 +73,6 @@ def __init__(self, platform):


class BaseSoC(SoCSDRAM):
default_platform = "kc705"

def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,