xilinx: change Spartan-6 DDR output alignment to C0

sbourdeauducq · sbourdeauducq · commit 11aa1be22df3 · 2017-08-16T15:04:00.000-06:00
diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py
@@ -130,7 +130,7 @@ def lower(dr):
 class XilinxDDROutputImplS6(Module):
     def __init__(self, i1, i2, o, clk):
         self.specials += Instance("ODDR2",
-                p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
+                p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="SYNC",
                 i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,
                 i_D0=i1, i_D1=i2, o_Q=o,
         )

Original file line number	Diff line number	Diff line change
`@@ -130,7 +130,7 @@ def lower(dr):`
`130`	`130`	`class XilinxDDROutputImplS6(Module):`
`131`	`131`	`def __init__(self, i1, i2, o, clk):`
`132`	`132`	`self.specials += Instance("ODDR2",`
`133`		`- p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",`
	`133`	`+ p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="SYNC",`
`134`	`134`	`i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,`
`135`	`135`	`i_D0=i1, i_D1=i2, o_Q=o,`
`136`	`136`	`)`