Skip to content

Commit

Permalink
xilinx: change Spartan-6 DDR output alignment to C0
Browse files Browse the repository at this point in the history
sbourdeauducq committed Aug 16, 2017
1 parent d8860cd commit 11aa1be
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion migen/build/xilinx/common.py
Original file line number Diff line number Diff line change
@@ -130,7 +130,7 @@ def lower(dr):
class XilinxDDROutputImplS6(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDR2",
p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="SYNC",
i_C0=clk, i_C1=~clk, i_CE=1, i_S=0, i_R=0,
i_D0=i1, i_D1=i2, o_Q=o,
)

0 comments on commit 11aa1be

Please sign in to comment.