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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: d8860cde6e3e
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 16, 2017

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    970428e View commit details
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Showing with 72 additions and 10 deletions.
  1. +68 −10 migen/build/xilinx/common.py
  2. +4 −0 migen/build/xilinx/platform.py
78 changes: 68 additions & 10 deletions migen/build/xilinx/common.py
Original file line number Diff line number Diff line change
@@ -119,7 +119,15 @@ def lower(dr):
return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)


class XilinxDDROutputImpl(Module):
xilinx_special_overrides = {
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
DifferentialInput: XilinxDifferentialInput,
DifferentialOutput: XilinxDifferentialOutput
}


class XilinxDDROutputImplS6(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDR2",
p_DDR_ALIGNMENT="NONE", p_INIT=0, p_SRTYPE="SYNC",
@@ -128,18 +136,14 @@ def __init__(self, i1, i2, o, clk):
)


class XilinxDDROutput:
class XilinxDDROutputS6:
@staticmethod
def lower(dr):
return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
return XilinxDDROutputImplS6(dr.i1, dr.i2, dr.o, dr.clk)


xilinx_special_overrides = {
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
DifferentialInput: XilinxDifferentialInput,
DifferentialOutput: XilinxDifferentialOutput,
DDROutput: XilinxDDROutput
xilinx_s6_special_overrides = {
DDROutput: XilinxDDROutputS6
}


@@ -158,6 +162,60 @@ def lower(dr):
return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk)


class XilinxDDRInputImplS7(Module):
def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDR",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
i_C=clk, i_CE=1, i_S=0, i_R=0,
o_D=i, i_Q1=o1, i_Q2=o2,
)


class XilinxDDRInputS7:
@staticmethod
def lower(dr):
return XilinxDDRInputImplS7(dr.i, dr.o1, dr.o2, dr.clk)


xilinx_s7_special_overrides = {
DDROutput: XilinxDDROutputS7
DDROutput: XilinxDDROutputS7,
DDRInput: XilinxDDRInputS7
}


class XilinxDDROutputImplKU(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRE1",
i_C=clk, i_SR=0,
i_D1=i1, i_D2=i2, o_Q=o,
)


class XilinxDDROutputKU:
@staticmethod
def lower(dr):
return XilinxDDROutputImplS7(dr.i1, dr.i2, dr.o, dr.clk)


class XilinxDDRInputImplKU(Module):
def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0,
i_d=i,
o_q1=o1, o_q2=o2,
i_c=clk, i_cb=~clk,
i_r=0
)


class XilinxDDRInputKU:
@staticmethod
def lower(dr):
return XilinxDDRInputImplS7(dr.i, dr.o1, dr.o2, dr.clk)


xilinx_ku_special_overrides = {
DDROutput: XilinxDDROutputKU,
DDRInput: XilinxDDRInputKU
}
4 changes: 4 additions & 0 deletions migen/build/xilinx/platform.py
Original file line number Diff line number Diff line change
@@ -16,8 +16,12 @@ def __init__(self, *args, toolchain="ise", **kwargs):

def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.xilinx_special_overrides)
if self.device[:3] == "xc6":
so.update(common.xilinx_s6_special_overrides)
if self.device[:3] == "xc7":
so.update(common.xilinx_s7_special_overrides)
if self.device[:4] == "xcku":
so.update(common.xilinx_ku_special_overrides)
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args,
special_overrides=so, attr_translate=self.toolchain.attr_translate, **kwargs)