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base repository: azonenberg/yosys
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head repository: azonenberg/yosys
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compare: 78fd24f40f1e
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Aug 14, 2017

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Showing with 66 additions and 2 deletions.
  1. +66 −2 techlibs/coolrunner2/cells_sim.v
68 changes: 66 additions & 2 deletions techlibs/coolrunner2/cells_sim.v
Original file line number Diff line number Diff line change
@@ -143,17 +143,21 @@ module BUFG(I, O);
endmodule

module BUFGSR(I, O);
parameter INVERT = 0;

input I;
output O;

assign O = I;
assign O = INVERT ? ~I : I;
endmodule

module BUFGTS(I, O);
parameter INVERT = 0;

input I;
output O;

assign O = I;
assign O = INVERT ? ~I : I;
endmodule

module FDDCP (C, PRE, CLR, D, Q);
@@ -244,3 +248,63 @@ module FTDCP (C, PRE, CLR, T, Q);

assign Q = Q_;
endmodule

module FDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;

input C, PRE, CLR, D, CE;
output reg Q;

initial begin
Q <= INIT;
end

always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule

module FDCPE_N (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;

input C, PRE, CLR, D, CE;
output reg Q;

initial begin
Q <= INIT;
end

always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule

module FDDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;

input C, PRE, CLR, D, CE;
output reg Q;

initial begin
Q <= INIT;
end

always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule