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/*********************************************************************************************************************** | ||
* Copyright (C) 2017 Andrew Zonenberg and contributors * | ||
* * | ||
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General * | ||
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) * | ||
* any later version. * | ||
* * | ||
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied * | ||
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for * | ||
* more details. * | ||
* * | ||
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may * | ||
* find one here: * | ||
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt * | ||
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software * | ||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA * | ||
**********************************************************************************************************************/ | ||
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`default_nettype none | ||
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/** | ||
TODO | ||
*/ | ||
module UART(txd, rxd); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// I/O declarations | ||
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(* LOC = "P9" *) //not yet used | ||
input wire rxd; | ||
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(* LOC = "P7" *) | ||
output reg txd = 0; | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Clocking | ||
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//The 2 MHz RC oscillator | ||
wire clk_250khz_cnt; //dedicated output to hard IP only | ||
wire clk_250khz; //general fabric output | ||
GP_RCOSC #( | ||
.PWRDN_EN(0), | ||
.AUTO_PWRDN(0), | ||
.OSC_FREQ("2M"), | ||
.HARDIP_DIV(8), | ||
.FABRIC_DIV(1) | ||
) rcosc ( | ||
.PWRDN(1'b0), | ||
.CLKOUT_HARDIP(clk_250khz_cnt), | ||
.CLKOUT_FABRIC(clk_250khz) | ||
); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Baud rate generator | ||
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localparam UART_BAUD = 9600; | ||
localparam CLOCK_FREQ = 250000; | ||
localparam UART_BDIV = CLOCK_FREQ / UART_BAUD; | ||
localparam UART_BMAX = UART_BDIV - 1; | ||
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reg[7:0] baud_count = UART_BMAX; | ||
wire baud_edge = (baud_count == 0); | ||
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reg sending = 0; | ||
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always @(posedge clk_250khz_cnt) begin | ||
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baud_count <= baud_count - 1'h1; | ||
if(baud_edge) | ||
baud_count <= UART_BMAX; | ||
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end | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Transmit counter | ||
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localparam MESSAGE_MAX = 14'h3fff; | ||
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reg[13:0] message_count = MESSAGE_MAX; | ||
wire message_edge = (message_count == 0); | ||
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always @(posedge clk_250khz_cnt) begin | ||
message_count <= message_count - 1'h1; | ||
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if(message_edge) | ||
message_count <= MESSAGE_MAX; | ||
end | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Pattern generator for the actual message we're sending | ||
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//Start bit is in LSB since that's what we output during reset. | ||
//High 7 bits of PGEN ignored, then bit-reversed payload | ||
wire txd_raw; | ||
GP_PGEN #( | ||
.PATTERN_LEN(5'd10), | ||
.PATTERN_DATA({7'h0, 8'h82, 1'h1}) | ||
) tx_pgen ( | ||
.nRST(!message_edge), | ||
.CLK(baud_edge), | ||
.OUT(txd_raw) | ||
); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Timer so we know how long the actual message lasts | ||
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localparam BYTE_MAX = 8'd10; | ||
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//Can't infer GP_COUNTx_ADV yet, so instantiate | ||
wire byte_done; | ||
GP_COUNT8_ADV #( | ||
.CLKIN_DIVIDE(1), | ||
.COUNT_TO(BYTE_MAX), | ||
.RESET_MODE("LEVEL"), | ||
.RESET_VALUE("COUNT_TO") | ||
) byte_count ( | ||
.CLK(clk_250khz_cnt), | ||
.RST(!sending), | ||
.UP(1'b0), | ||
.KEEP(!baud_edge), | ||
.OUT(byte_done), | ||
.POUT() | ||
); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Send logic | ||
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reg send_pending = 0; | ||
always @(posedge clk_250khz) begin | ||
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if(message_edge) begin | ||
send_pending <= 1; | ||
end | ||
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if(send_pending && baud_edge) begin | ||
send_pending <= 0; | ||
sending <= 1; | ||
end | ||
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if(byte_done) begin | ||
sending <= 0; | ||
end | ||
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if(sending) | ||
txd <= txd_raw; | ||
else | ||
txd <= 1; | ||
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end | ||
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endmodule |