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Commit 6f4420d

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azonenbergazonenberg
committedAug 15, 2017
Added UART test
1 parent b5d38c9 commit 6f4420d

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Diff for: ‎tests/greenpak4/slg46620v/CMakeLists.txt

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@@ -14,6 +14,7 @@ add_greenpak4_bitstream(Loop SLG46620V)
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add_greenpak4_bitstream(POR SLG46620V)
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add_greenpak4_bitstream(SPIToDCMP SLG46620V)
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add_greenpak4_bitstream(Tristate SLG46620V)
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add_greenpak4_bitstream(UART SLG46620V)
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add_greenpak4_bitstream(Vector SLG46620V)
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add_greenpak4_bitstream(VrefEXT SLG46620V)
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add_greenpak4_bitstream(VrefVDD SLG46620V)

Diff for: ‎tests/greenpak4/slg46620v/UART.v

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/***********************************************************************************************************************
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* Copyright (C) 2017 Andrew Zonenberg and contributors *
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* *
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* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
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* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
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* any later version. *
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* *
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* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
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* more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
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* find one here: *
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* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
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* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
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**********************************************************************************************************************/
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`default_nettype none
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/**
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TODO
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*/
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module UART(txd, rxd);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// I/O declarations
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(* LOC = "P9" *) //not yet used
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input wire rxd;
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(* LOC = "P7" *)
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output reg txd = 0;
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Clocking
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//The 2 MHz RC oscillator
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wire clk_250khz_cnt; //dedicated output to hard IP only
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wire clk_250khz; //general fabric output
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GP_RCOSC #(
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.PWRDN_EN(0),
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.AUTO_PWRDN(0),
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.OSC_FREQ("2M"),
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.HARDIP_DIV(8),
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.FABRIC_DIV(1)
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) rcosc (
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.PWRDN(1'b0),
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.CLKOUT_HARDIP(clk_250khz_cnt),
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.CLKOUT_FABRIC(clk_250khz)
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Baud rate generator
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localparam UART_BAUD = 9600;
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localparam CLOCK_FREQ = 250000;
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localparam UART_BDIV = CLOCK_FREQ / UART_BAUD;
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localparam UART_BMAX = UART_BDIV - 1;
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reg[7:0] baud_count = UART_BMAX;
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wire baud_edge = (baud_count == 0);
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reg sending = 0;
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always @(posedge clk_250khz_cnt) begin
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baud_count <= baud_count - 1'h1;
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if(baud_edge)
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baud_count <= UART_BMAX;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Transmit counter
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localparam MESSAGE_MAX = 14'h3fff;
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reg[13:0] message_count = MESSAGE_MAX;
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wire message_edge = (message_count == 0);
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always @(posedge clk_250khz_cnt) begin
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message_count <= message_count - 1'h1;
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if(message_edge)
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message_count <= MESSAGE_MAX;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Pattern generator for the actual message we're sending
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//Start bit is in LSB since that's what we output during reset.
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//High 7 bits of PGEN ignored, then bit-reversed payload
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wire txd_raw;
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GP_PGEN #(
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.PATTERN_LEN(5'd10),
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.PATTERN_DATA({7'h0, 8'h82, 1'h1})
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) tx_pgen (
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.nRST(!message_edge),
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.CLK(baud_edge),
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.OUT(txd_raw)
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Timer so we know how long the actual message lasts
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localparam BYTE_MAX = 8'd10;
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//Can't infer GP_COUNTx_ADV yet, so instantiate
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wire byte_done;
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GP_COUNT8_ADV #(
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.CLKIN_DIVIDE(1),
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.COUNT_TO(BYTE_MAX),
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.RESET_MODE("LEVEL"),
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.RESET_VALUE("COUNT_TO")
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) byte_count (
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.CLK(clk_250khz_cnt),
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.RST(!sending),
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.UP(1'b0),
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.KEEP(!baud_edge),
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.OUT(byte_done),
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.POUT()
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);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// Send logic
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reg send_pending = 0;
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always @(posedge clk_250khz) begin
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if(message_edge) begin
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send_pending <= 1;
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end
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if(send_pending && baud_edge) begin
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send_pending <= 0;
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sending <= 1;
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end
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if(byte_done) begin
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sending <= 0;
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end
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if(sending)
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txd <= txd_raw;
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else
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txd <= 1;
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end
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endmodule

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