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base repository: azonenberg/yosys
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base: 24cbc324967a^
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head repository: azonenberg/yosys
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compare: cc82845dedb0
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- 10 commits
- 6 files changed
- 1 contributor
Commits on Aug 14, 2017
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recover_adder_core: Initial commit
The code seems to correctly traverse adder chains and terminates correctly. The code to add $add/$sub/$alu has not yet been written.
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recover_adder_core: Generate $add/$sub in the simple case
$add can be generated as long as there is no carry-in or fanouts on the carry signals. $sub currently is only implemented if there is neither a carry-in nor a carry-out.
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recover_adder: Replace XOR3 and MAJ gates with structural Verilog
This way, they generate the uppercase cells rather than the lowercase cells, and it is possible to directly run abc afterwards. Before this change, it would be necessary to run simplemap first, which might destroy some other cells that have been recovered.
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