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base repository: m-labs/misoc
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base: 739e41b5fe55
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head repository: m-labs/misoc
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compare: 504775c561fa
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  • 4 commits
  • 3 files changed
  • 1 contributor

Commits on Aug 25, 2016

  1. Copy the full SHA
    01fa9ad View commit details
  2. Copy the full SHA
    107db16 View commit details
  3. cores/spi: adapt to new misoc API, fix tests

    spi: Fix imports for testbench, new misoc API.
    
    Full test suite runs without runtime errors (some tests fail).
    
    Rework old test suite into something usable. Core passes without error.
    cr1901 authored and jordens committed Aug 25, 2016
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    17c8fc9 View commit details
  4. cores/spi: replace wb interface with csr interface

    bus => wbus to prepare CSR replacement.
    
    Replace data write/data read regs with CSR equivalents.
    
    Fix combinational logic error.
    
    Convert wishbone xfer reg into CSR equivalents.
    
    Convert config register to CSR. Pending not working.
    
    Fix broken register definitions in test suite.
    
    Pending status needs to be asserted one cycle earlier so that it is valid
    immediately after write.
    
    Remove wishbone bus from core/test files.
    
    Variable name cleanup (Remove CSR qualifiers).
    
    User friendly register names, minor test suite reg assignment changes (does
    not affect results).
    
    Update/run full test suite for CSR. Core passes.
    
    Update inline documentation of SPI API.
    
    Remove wishbone import.
    
    Remove description of CSR registers.
    
    _device_sel => _cs, device_width => cs_width.
    
    Remove status record, split status reg into multiple.
    
    Remove config record, split config reg into multiple.
    
    Update reg names in Notes.
    
    Python 3.3/3.4 syntax fix for tests.
    
    Remove complex pending logic.
    
    PEP8 cleanup (If/Else statements not changed).
    cr1901 authored and jordens committed Aug 25, 2016
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    504775c View commit details
Showing with 475 additions and 203 deletions.
  1. +1 −1 misoc/cores/spi/__init__.py
  2. +288 −125 misoc/cores/spi/core.py
  3. +186 −77 misoc/cores/spi/test.py
2 changes: 1 addition & 1 deletion misoc/cores/spi/__init__.py
Original file line number Diff line number Diff line change
@@ -1 +1 @@
from misoc.spi.core import SPIMaster
from misoc.cores.spi.core import SPIMaster
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