Files:
    new file:   gateware/vga/__init__.py
    new file:   gateware/vga/analysis.py
    new file:   gateware/vga/datacapture.py

__init__.py:
    Implements VGAIn module which instantiates submodules
    Datacapture, FrameExtrantion and DMA, and connects them

analysis.py:
    Implements FrameExtraction module, which is reponsible
    for sof(start of frame) detection, color space conversion,
    framing(packing) and also uses async fifo to move data
    from VGA pixel clock domain to sys_clk domain

datacapture.py:
    Implements DataCapture module which is responsible for
    capturing pixel data at proper time, depending on HSYNC
    and VSYNC signals

Currently only supports 1024x768@60Hz resolution capture

Ideally should have used _connectors interface?

VGAIn modules gives VGA capture functionality to atlys. Also, we
are now inheriting BaseSoC class directly instead of MinoSoC class
because VGA signals' 3.3V logic-level conflicts with ethernet's
2.5V logic-level. MiniSoC instantiates ethernet modules so we are
bypassing it and inheriting BaseSoC class.