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  • 7 commits
  • 1 file changed
  • 1 contributor

Commits on Aug 7, 2016

  1. VCCAUX is actually 3.3V on the Atlys. 

    See Sheet 10 - FPGA POWER
 - https://reference.digilentinc.com/_media/atlys:atlys:atlys_sch.pdf
    @mithro
    mithro committed Aug 7, 2016
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    8868807 View commit details

  2. Make VCCB2 configurable as 2V5 or 3V3.

    @mithro
    mithro committed Aug 7, 2016
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    808104c View commit details

  3. Each bank has one voltage level.

    @mithro
    mithro committed Aug 7, 2016
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    22bff28 View commit details

  4. Fixing voltage level for SCL/SDA.

    @mithro
    mithro committed Aug 7, 2016
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    b0a9613 View commit details

  5. Making the default voltage level 3V3.

    @mithro
    mithro committed Aug 7, 2016
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    b4987a4 View commit details

  6. Some parts only work at a given VCCB2 level.

    @mithro
    mithro committed Aug 7, 2016
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  7. Merge pull request #280 from mithro/atlys-vccb2-fix 

    Rework IO standards for Atlys board
    @mithro
    mithro authored Aug 7, 2016
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    e4f99d8 View commit details
Showing with 106 additions and 49 deletions.
  1. +106 −49 platforms/atlys.py
155 changes: 106 additions & 49 deletions platforms/atlys.py
View file
Original file line number Diff line number Diff line change
@@ -13,17 +13,57 @@

# There appear to be 4 x LTC2481C on the U1-SCL / U1-SDA lines connected to the Cypress

class DynamicLVCMOS(object):
"""Object to allow configuration of IOBs connected to dynamic voltage level.
This is used because VCCB2 supply for Bank 2 can be connected to either the
VCC2V5 or VCC3V3 rail depending on JP12, however there is no way to
autodetect this.
"""

def __init__(self, name):
self.name = name
self.level = None

def set(self, value):
self.level = {
"VCC2V5": "LVCMOS25",
"VCC3V3": "LVCMOS33",
}[value]

def __str__(self):
assert self.level, "%s object accessed before voltage level set!" % self.name
return self.level

def __add__(self, o):
return str(self) + o

def __radd__(self, o):
return o + str(self)


# VCC Bank 0 == 3V3
LVCMOS_BANK0 = "LVCMOS33"
# VCC Bank 1 == 3V3
LVCMOS_BANK1 = "LVCMOS33"
# VCC Bank 2 == 3V3 or 2V5
LVCMOS_BANK2 = DynamicLVCMOS("LVCMOS_BANK2")
# VCC Bank 3 == 1V8
LVCMOS_BANK3 = "LVCMOS18"
# VCC Aux == 3V3


_io = [
# NET "clk" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
# SG8002JF - 100MHz - CMOS Crystal Oscillator
("clk100", 0, Pins("L15"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("L15"), IOStandard(LVCMOS_BANK1)),

# M0/RESET button
# VCCB2 --[10K]--+--[1k]-- M0/Reset
# |
# GND -[ BTN ]-+--[390]- BTNRST
# NET "btn<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
("cpu_reset", 0, Pins("T15"), IOStandard("LVCMOS25")),
("cpu_reset", 0, Pins("T15"), IOStandard(LVCMOS_BANK2)),

## onBoard USB controller - FIXME
# CY7C68013A-56
@@ -54,7 +94,7 @@
Subsignal("oe_n", Pins("A15"), Misc("DRIVE=12")),
Subsignal("cs_n", Pins("B2")),
Subsignal("pktend_n", Pins("C4"), Misc("DRIVE=12")),
IOStandard("LVCMOS33")
IOStandard(LVCMOS_BANK0)
),

## onBoard Quad-SPI Flash
@@ -73,7 +113,7 @@
# NET "FlashMemDq<2>" LOC = "T14"; # Bank = 2, Pin name = IO_L12P_D1_MISO2_2, Sch name = DQ2
# NET "FlashMemDq<3>" LOC = "V14"; # Bank = 2, Pin name = IO_L12N_D2_MISO3_2, Sch name = DQ3
Subsignal("dq", Pins("T13", "R13", "T14", "V14")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
IOStandard(LVCMOS_BANK2), Misc("SLEW=FAST")
),

## onBoard Leds
@@ -85,28 +125,28 @@
# NET "Led<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
# NET "Led<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
# NET "Led<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
("user_led", 0, Pins("U18")),
("user_led", 1, Pins("M14")),
("user_led", 2, Pins("N14")),
("user_led", 3, Pins("L14")),
("user_led", 4, Pins("M13")),
("user_led", 5, Pins("D4"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("P16")),
("user_led", 7, Pins("N12")),
("user_led", 0, Pins("U18"), IOStandard(LVCMOS_BANK1)),
("user_led", 1, Pins("M14"), IOStandard(LVCMOS_BANK1)),
("user_led", 2, Pins("N14"), IOStandard(LVCMOS_BANK1)),
("user_led", 3, Pins("L14"), IOStandard(LVCMOS_BANK1)),
("user_led", 4, Pins("M13"), IOStandard(LVCMOS_BANK1)),
("user_led", 5, Pins("D4"), IOStandard(LVCMOS_BANK0)),
("user_led", 6, Pins("P16"), IOStandard(LVCMOS_BANK1)),
("user_led", 7, Pins("N12"), IOStandard(LVCMOS_BANK2)),

## onBoard PUSH BUTTONS - FIXME
# Mapping "up" to north
# VCC1V8 - pulled down to GND via 10k
# NET "btn<1>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU
("user_btn_n", 0, Pins("N4"), IOStandard("LVCMOS18")),
("user_btn_n", 0, Pins("N4"), IOStandard(LVCMOS_BANK3)),
# NET "btn<2>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL
("user_btn_e", 0, Pins("P4"), IOStandard("LVCMOS18")),
("user_btn_e", 1, Pins("P4"), IOStandard(LVCMOS_BANK3)),
# NET "btn<3>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND
("user_btn_s", 0, Pins("P3"), IOStandard("LVCMOS18")),
("user_btn_s", 2, Pins("P3"), IOStandard(LVCMOS_BANK3)),
# NET "btn<4>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR
("user_btn_w", 0, Pins("F6"), IOStandard("LVCMOS18")),
("user_btn_w", 3, Pins("F6"), IOStandard(LVCMOS_BANK3)),
# NET "btn<5>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC
("user_btn_c", 0, Pins("F5"), IOStandard("LVCMOS18")),
("user_btn_c", 4, Pins("F5"), IOStandard(LVCMOS_BANK3)),

## onBoard SWITCHES - FIXME
# SW(0,1,2,3) - VCC3V3 / GND
@@ -120,14 +160,14 @@
# NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
# NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
# NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
("user_dip", 0, Pins("A10"), IOStandard("LVCMOS33")),
("user_dip", 1, Pins("D14"), IOStandard("LVCMOS33")),
("user_dip", 2, Pins("C14"), IOStandard("LVCMOS33")),
("user_dip", 3, Pins("P15"), IOStandard("LVCMOS33")),
("user_dip", 4, Pins("P12"), IOStandard("LVCMOS33")),
("user_dip", 5, Pins("R5"), IOStandard("LVCMOS33")),
("user_dip", 6, Pins("T5"), IOStandard("LVCMOS33")),
("user_dip", 7, Pins("E4"), IOStandard("LVCMOS18")),
("user_dip", 0, Pins("A10"), IOStandard(LVCMOS_BANK0)),
("user_dip", 1, Pins("D14"), IOStandard(LVCMOS_BANK0)),
("user_dip", 2, Pins("C14"), IOStandard(LVCMOS_BANK0)),
("user_dip", 3, Pins("P15"), IOStandard(LVCMOS_BANK1)),
("user_dip", 4, Pins("P12"), IOStandard(LVCMOS_BANK2)),
("user_dip", 5, Pins("R5"), IOStandard(LVCMOS_BANK2)),
("user_dip", 6, Pins("T5"), IOStandard(LVCMOS_BANK2)),
("user_dip", 7, Pins("E4"), IOStandard(LVCMOS_BANK3)),

## TEMAC Ethernet MAC - FIXME
# 10/100/1000 Ethernet PHY
@@ -141,7 +181,7 @@
Subsignal("gtx", Pins("L12")),
# NET "phyrxclk" LOC = "K15"; # Bank = 1, Pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = E-RXCLK
Subsignal("rx", Pins("K15")),
IOStandard("LVCMOS25")
IOStandard(LVCMOS_BANK1)
),
("eth", 0,
# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET
@@ -182,7 +222,7 @@
Subsignal("col", Pins("C17")),
# C18 - from Atlys reference manual, not listed in UCF file?
Subsignal("crs", Pins("C18")),
IOStandard("LVCMOS25")
IOStandard(LVCMOS_BANK1)
),

## DDR2
@@ -322,8 +362,8 @@
Subsignal("data2_p", Pins("B12")),
Subsignal("data2_n", Pins("A12")),
# Make sure JP2 is connected. Shared with J1.
Subsignal("scl", Pins("C13"), IOStandard("LVCMOS25")),
Subsignal("sda", Pins("A13"), IOStandard("LVCMOS33")),
Subsignal("scl", Pins("C13"), IOStandard(LVCMOS_BANK0)),
Subsignal("sda", Pins("A13"), IOStandard(LVCMOS_BANK0)),
#Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")),
#Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33"))
),
@@ -355,8 +395,8 @@
Subsignal("data2_n", Pins("J18")),
# Disconnect JP6 and JP7 for FPGA SCL/SDA control, otherwise
# this is connected to J2's SCL/SDA pins.
Subsignal("scl", Pins("M16"), IOStandard("LVCMOS25")),
Subsignal("sda", Pins("M18"), IOStandard("LVCMOS25")),
Subsignal("scl", Pins("M16"), IOStandard(LVCMOS_BANK1)),
Subsignal("sda", Pins("M18"), IOStandard(LVCMOS_BANK1)),
#Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")),
#Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33"))
),
@@ -396,6 +436,24 @@
Subsignal("tx", Pins("B16"), IOStandard("LVCMOS33")),
),

# ("fpga_cfg",
# Subsignal("din", Pins("T14")),
# Subsignal("cclk", Pins("R14")),
# Subsignal("init_b", Pins("T12")),
# Subsignal("prog_b", Pins("A2")),
# Subsignal("done", Pins("T15")),
# ),
# ("jtag",
# Subsignal("tms", Pins("B2")),
# Subsignal("tdo", Pins("B16")),
# Subsignal("tdi", Pins("B1")),
# Subsignal("tck", Pins("A15")),
# ),

]

# This Micro-D HDMI connector only works when VCCB2 is set to 3V3.
_io_vccb2_3v3 = [
## PMOD Connector
# Micro-D connector, marked as JB, on the same side as switches + LEDs
# but on the underside of the board below MOD connector. Works as
@@ -426,23 +484,10 @@
#Subsignal("scl", Pins("C13"), IOStandard("LVCMOS33")),
#Subsignal("sda", Pins("A13"), IOStandard("LVCMOS33")),
),

# ("fpga_cfg",
# Subsignal("din", Pins("T14")),
# Subsignal("cclk", Pins("R14")),
# Subsignal("init_b", Pins("T12")),
# Subsignal("prog_b", Pins("A2")),
# Subsignal("done", Pins("T15")),
# ),
# ("jtag",
# Subsignal("tms", Pins("B2")),
# Subsignal("tdo", Pins("B16")),
# Subsignal("tdi", Pins("B1")),
# Subsignal("tck", Pins("A15")),
# ),

]

_io_vccb2_2v5 = []

_connectors = [
## onboard VHDCI - FIXME
# Can either run at 2.5V or 3.3V dependent on JP12 connector.
@@ -594,13 +639,25 @@ class Platform(XilinxPlatform):
gateware_size = 0x200000


def __init__(self, programmer="openocd"):
def __init__(self, programmer="openocd", vccb2_voltage="VCC3V3"):
# Some IO configurations only work at certain vccb2 voltages.
if vccb2_voltage == "VCC3V3":
_io.extend(_io_vccb2_3v3)
elif vccb2_voltage == "VCC2V5":
_io.extend(_io_vccb2_2v5)
else:
raise SystemError("Unknown vccb2_voltage=%r" % vccb2_voltage)

# Resolve the LVCMOS_BANK2 voltage level before anything uses the _io
# definition.
LVCMOS_BANK2.set(vccb2_voltage)

# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer

# FPGA AUX is connected to the 2.5V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="2.5";""")
# FPGA AUX is connected to the 3.3V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="3.3";""")

def create_programmer(self):
# Preferred programmer - Needs ixo-usb-jtag and latest openocd.