Fix bug loading libraries when they are already loaded

ArcaneNibble · azonenberg · commit 5fd9c2a0f87b · 2017-08-30T16:31:36.000-07:00
diff --git a/passes/techmap/extract_tff.cc b/passes/techmap/extract_tff.cc
@@ -45,16 +45,21 @@ struct ExtractTFFPass : public ScriptPass
     }
 
     bool no_final_abc;
+    bool already_loaded_lib;
 
     virtual void clear_flags() YS_OVERRIDE
     {
         no_final_abc = false;
+        already_loaded_lib = false;
     }
 
     virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
     {
         clear_flags();
 
+        if (design->has("\\__TFF_N_"))
+            already_loaded_lib = true;
+
         size_t argidx;
         for (argidx = 1; argidx < args.size(); argidx++)
         {
@@ -78,7 +83,9 @@ struct ExtractTFFPass : public ScriptPass
     {
         run("abc -g AND,XOR");
         run("extract -map +/untechmap/tff_untechmap.v");
-        run("read_verilog -lib +/untechmap/tff_untechmap.v");
+        // Load this library only if the design doesn't already have it
+        if (!already_loaded_lib)
+            run("read_verilog -lib +/untechmap/tff_untechmap.v");
 
         if (!no_final_abc)
             run("abc");

Original file line number	Diff line number	Diff line change
`@@ -45,16 +45,21 @@ struct ExtractTFFPass : public ScriptPass`
`45`	`45`	`}`
`46`	`46`
`47`	`47`	`bool no_final_abc;`
	`48`	`+ bool already_loaded_lib;`
`48`	`49`
`49`	`50`	`virtual void clear_flags() YS_OVERRIDE`
`50`	`51`	`{`
`51`	`52`	`no_final_abc = false;`
	`53`	`+ already_loaded_lib = false;`
`52`	`54`	`}`
`53`	`55`
`54`	`56`	`virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE`
`55`	`57`	`{`
`56`	`58`	`clear_flags();`
`57`	`59`
	`60`	`+ if (design->has("\\__TFF_N_"))`
	`61`	`+ already_loaded_lib = true;`
	`62`	`+`
`58`	`63`	`size_t argidx;`
`59`	`64`	`for (argidx = 1; argidx < args.size(); argidx++)`
`60`	`65`	`{`
`@@ -78,7 +83,9 @@ struct ExtractTFFPass : public ScriptPass`
`78`	`83`	`{`
`79`	`84`	`run("abc -g AND,XOR");`
`80`	`85`	`run("extract -map +/untechmap/tff_untechmap.v");`
`81`		`- run("read_verilog -lib +/untechmap/tff_untechmap.v");`
	`86`	`+ // Load this library only if the design doesn't already have it`
	`87`	`+ if (!already_loaded_lib)`
	`88`	`+ run("read_verilog -lib +/untechmap/tff_untechmap.v");`
`82`	`89`
`83`	`90`	`if (!no_final_abc)`
`84`	`91`	`run("abc");`