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Merge branch 'master' of https://github.com/cliffordwolf/yosys into r…
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…ecover_adder
azonenberg committed Aug 30, 2017
2 parents 30d9fbc + c0034f5 commit ad975af
Showing 24 changed files with 3,051 additions and 567 deletions.
68 changes: 34 additions & 34 deletions backends/smt2/smt2.cc
Original file line number Diff line number Diff line change
@@ -794,6 +794,40 @@ struct Smt2Worker
}
}

if (verbose) log("=> export logic driving hierarchical cells\n");

for (auto cell : module->cells())
if (module->design->module(cell->type) != nullptr)
export_cell(cell);

while (!hiercells_queue.empty())
{
std::set<RTLIL::Cell*> queue;
queue.swap(hiercells_queue);

for (auto cell : queue)
{
string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
Module *m = module->design->module(cell->type);
log_assert(m != nullptr);

for (auto &conn : cell->connections())
{
Wire *w = m->wire(conn.first);
SigSpec sig = sigmap(conn.second);

if (bvmode || GetSize(w) == 1) {
hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
} else {
for (int i = 0; i < GetSize(w); i++)
hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
}
}
}
}

for (int iter = 1; !registers.empty(); iter++)
{
pool<Cell*> this_regs;
@@ -940,40 +974,6 @@ struct Smt2Worker
}
}

if (verbose) log("=> export logic driving hierarchical cells\n");

for (auto cell : module->cells())
if (module->design->module(cell->type) != nullptr)
export_cell(cell);

while (!hiercells_queue.empty())
{
std::set<RTLIL::Cell*> queue;
queue.swap(hiercells_queue);

for (auto cell : queue)
{
string cell_state = stringf("(|%s_h %s| state)", get_id(module), get_id(cell->name));
Module *m = module->design->module(cell->type);
log_assert(m != nullptr);

for (auto &conn : cell->connections())
{
Wire *w = m->wire(conn.first);
SigSpec sig = sigmap(conn.second);

if (bvmode || GetSize(w) == 1) {
hier.push_back(stringf(" (= %s (|%s_n %s| %s)) ; %s.%s\n", (GetSize(w) > 1 ? get_bv(sig) : get_bool(sig)).c_str(),
get_id(cell->type), get_id(w), cell_state.c_str(), get_id(cell->type), get_id(w)));
} else {
for (int i = 0; i < GetSize(w); i++)
hier.push_back(stringf(" (= %s (|%s_n %s %d| %s)) ; %s.%s[%d]\n", get_bool(sig[i]).c_str(),
get_id(cell->type), get_id(w), i, cell_state.c_str(), get_id(cell->type), get_id(w), i));
}
}
}
}

if (verbose) log("=> finalizing SMT2 representation of %s.\n", log_id(module));

for (auto c : hiercells) {
1 change: 1 addition & 0 deletions frontends/json/jsonparse.cc
Original file line number Diff line number Diff line change
@@ -271,6 +271,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->port_output = true;
} else
if (port_direction_node->data_string == "inout") {
port_wire->port_input = true;
port_wire->port_output = true;
} else
log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str());
4 changes: 4 additions & 0 deletions kernel/celltypes.h
Original file line number Diff line number Diff line change
@@ -322,6 +322,10 @@ struct CellTypes
return const_xor(arg1, arg2, false, false, 1);
if (type == "$_XNOR_")
return const_xnor(arg1, arg2, false, false, 1);
if (type == "$_ANDNOT_")
return const_and(arg1, eval_not(arg2), false, false, 1);
if (type == "$_ORNOT_")
return const_or(arg1, eval_not(arg2), false, false, 1);

log_abort();
}
7 changes: 7 additions & 0 deletions kernel/hashlib.h
Original file line number Diff line number Diff line change
@@ -868,6 +868,13 @@ class pool
return !operator==(other);
}

bool hash() const {
unsigned int hashval = mkhash_init;
for (auto &it : entries)
hashval ^= ops.hash(it.udata);
return hashval;
}

void reserve(size_t n) { entries.reserve(n); }
size_t size() const { return entries.size(); }
bool empty() const { return entries.empty(); }
49 changes: 49 additions & 0 deletions kernel/rtlil.cc
Original file line number Diff line number Diff line change
@@ -161,6 +161,39 @@ std::string RTLIL::Const::decode_string() const
return string;
}

bool RTLIL::Const::is_fully_zero() const
{
cover("kernel.rtlil.const.is_fully_zero");

for (auto bit : bits)
if (bit != RTLIL::State::S0)
return false;

return true;
}

bool RTLIL::Const::is_fully_def() const
{
cover("kernel.rtlil.const.is_fully_def");

for (auto bit : bits)
if (bit != RTLIL::State::S0 && bit != RTLIL::State::S1)
return false;

return true;
}

bool RTLIL::Const::is_fully_undef() const
{
cover("kernel.rtlil.const.is_fully_undef");

for (auto bit : bits)
if (bit != RTLIL::State::Sx && bit != RTLIL::State::Sz)
return false;

return true;
}

void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id)
{
attributes[id] = RTLIL::Const(1);
@@ -201,6 +234,22 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
return data;
}

void RTLIL::AttrObject::set_src_attribute(const std::string &src)
{
if (src.empty())
attributes.erase("\\src");
else
attributes["\\src"] = src;
}

std::string RTLIL::AttrObject::get_src_attribute() const
{
std::string src;
if (attributes.count("\\src"))
src = attributes.at("\\src").decode_string();
return src;
}

bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)
8 changes: 8 additions & 0 deletions kernel/rtlil.h
Original file line number Diff line number Diff line change
@@ -479,6 +479,10 @@ struct RTLIL::Const
inline RTLIL::State &operator[](int index) { return bits.at(index); }
inline const RTLIL::State &operator[](int index) const { return bits.at(index); }

bool is_fully_zero() const;
bool is_fully_def() const;
bool is_fully_undef() const;

inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const {
RTLIL::Const ret;
ret.bits.reserve(len);
@@ -501,9 +505,13 @@ struct RTLIL::AttrObject

void set_bool_attribute(RTLIL::IdString id);
bool get_bool_attribute(RTLIL::IdString id) const;

void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
void add_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
pool<string> get_strpool_attribute(RTLIL::IdString id) const;

void set_src_attribute(const std::string &src);
std::string get_src_attribute() const;
};

struct RTLIL::SigChunk
40 changes: 38 additions & 2 deletions passes/cmds/select.cc
Original file line number Diff line number Diff line change
@@ -1482,17 +1482,53 @@ struct CdPass : public Pass {
log("\n");
log(" cd ..\n");
log("\n");
log("Remove trailing substrings that start with '.' in current module name until\n");
log("the name of a module in the current design is generated, then switch to that\n");
log("module. Otherwise clear the current selection.\n");
log("\n");
log(" cd\n");
log("\n");
log("This is just a shortcut for 'select -clear'.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
if (args.size() != 2)
if (args.size() != 1 && args.size() != 2)
log_cmd_error("Invalid number of arguments.\n");

if (args[1] == "..") {
if (args.size() == 1 || args[1] == "/") {
design->selection_stack.back() = RTLIL::Selection(true);
design->selected_active_module = std::string();
return;
}

if (args[1] == "..")
{
string modname = design->selected_active_module;

design->selection_stack.back() = RTLIL::Selection(true);
design->selected_active_module = std::string();

while (1)
{
size_t pos = modname.rfind('.');

if (pos == string::npos)
break;

modname = modname.substr(0, pos);
Module *mod = design->module(modname);

if (mod == nullptr)
continue;

design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
design->selection_stack.back().optimize(design);
return;
}

return;
}

3 changes: 0 additions & 3 deletions passes/fsm/fsm_map.cc
Original file line number Diff line number Diff line change
@@ -274,9 +274,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width);
RTLIL::SigSpec sig_b, sig_s;
int reset_state = fsm_data.reset_state;
if (reset_state < 0)
reset_state = 0;

for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
RTLIL::Const state = fsm_data.state_table[i];
2 changes: 1 addition & 1 deletion passes/hierarchy/Makefile.inc
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@

OBJS += passes/hierarchy/hierarchy.o
OBJS += passes/hierarchy/singleton.o
OBJS += passes/hierarchy/uniquify.o
OBJS += passes/hierarchy/submod.o

39 changes: 20 additions & 19 deletions passes/hierarchy/singleton.cc → passes/hierarchy/uniquify.cc
Original file line number Diff line number Diff line change
@@ -22,28 +22,28 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct SingletonPass : public Pass {
SingletonPass() : Pass("singleton", "create singleton modules") { }
struct UniquifyPass : public Pass {
UniquifyPass() : Pass("uniquify", "create unique copies of modules") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" singleton [selection]\n");
log(" uniquify [selection]\n");
log("\n");
log("By default, a module that is instantiated by several other modules is only\n");
log("kept once in the design. This preserves the original modularity of the design\n");
log("and reduces the overall size of the design in memory. But it prevents certain\n");
log("optimizations and other operations on the design. This pass creates singleton\n");
log("optimizations and other operations on the design. This pass creates unique\n");
log("modules for all selected cells. The created modules are marked with the\n");
log("'singleton' attribute.\n");
log("'unique' attribute.\n");
log("\n");
log("This commands only operates on modules that by themself have the 'singleton'\n");
log("attribute set (the 'top' module is a singleton implicitly).\n");
log("This commands only operates on modules that by themself have the 'unique'\n");
log("attribute set (the 'top' module is unique implicitly).\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header(design, "Executing SINGLETON pass (creating singleton modules).\n");
log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");

size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -56,46 +56,47 @@ struct SingletonPass : public Pass {
extra_args(args, argidx, design);

bool did_something = true;
int singleton_cnt = 0;
int count = 0;

while (did_something)
{
did_something = false;

for (auto module : design->selected_modules())
{
if (!module->get_bool_attribute("\\singleton") && !module->get_bool_attribute("\\top"))
if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute("\\top"))
continue;

for (auto cell : module->selected_cells())
{
auto tmod = design->module(cell->type);
Module *tmod = design->module(cell->type);
IdString newname = module->name.str() + "." + log_id(cell->name);

if (tmod == nullptr)
continue;

if (tmod->get_bool_attribute("\\blackbox"))
continue;

if (tmod->get_bool_attribute("\\singleton"))
if (tmod->get_bool_attribute("\\unique") && newname == tmod->name)
continue;

cell->type = module->name.str() + "." + log_id(cell->name);
log("Creating singleton '%s'.\n", log_id(cell->type));
log("Creating module %s from %s.\n", log_id(newname), log_id(tmod));

auto smod = tmod->clone();
smod->name = cell->type;
smod->set_bool_attribute("\\singleton");
smod->name = newname;
cell->type = newname;
smod->set_bool_attribute("\\unique");
design->add(smod);

did_something = true;
singleton_cnt++;
count++;
}
}
}

log("Created %d singleton modules.\n", singleton_cnt);
log("Created %d unique modules.\n", count);
}
} SingletonPass;
} UniquifyPass;

PRIVATE_NAMESPACE_END
1 change: 1 addition & 0 deletions passes/opt/Makefile.inc
Original file line number Diff line number Diff line change
@@ -6,6 +6,7 @@ OBJS += passes/opt/opt_reduce.o
OBJS += passes/opt/opt_rmdff.o
OBJS += passes/opt/opt_clean.o
OBJS += passes/opt/opt_expr.o
OBJS += passes/opt/rmports.o

ifneq ($(SMALL),1)
OBJS += passes/opt/share.o
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