spi: fix handling of half-duplex+multi-bus combination

sbourdeauducq · sbourdeauducq · commit 3bd95ce0c178 · 2017-08-31T12:15:17.000+08:00
diff --git a/misoc/cores/spi.py b/misoc/cores/spi.py
@@ -315,6 +315,8 @@ def __init__(self, pads, data_width=32, clock_width=8, bits_width=6):
             ]
             offset += len(pads.cs_n)
 
+        miso_r = 0
+        mosi_t_i_r = 0
         for pads in pads_list:
             clk_t = TSTriple()
             self.specials += clk_t.get_tristate(pads.clk)
@@ -330,9 +332,7 @@ def __init__(self, pads, data_width=32, clock_width=8, bits_width=6):
                             (spi.oe | ~self._half_duplex.storage)),
                 mosi_t.o.eq(spi.reg.o),
             ]
+            miso_r |= getattr(pads, "miso", 0)
+            mosi_t_i_r |= mosi_t.i
 
-        if all(hasattr(pads, "miso") for pads in pads_list):
-            miso = reduce(or_, [pads.miso for pads in pads_list])
-        else:
-            miso = mosi_t.i
-        self.comb += spi.reg.i.eq(Mux(self._half_duplex.storage, mosi_t.i, miso))
+        self.comb += spi.reg.i.eq(Mux(self._half_duplex.storage, mosi_t_i_r, miso_r))
