migen: add second SPI flash, RTM serial, and second serial

m-labs · Aug 20, 2017 · f392ad2 · f392ad2
1 parent 38fe2f9
commit f392ad2
Showing 1 changed file with 18 additions and 0 deletions.
diff --git a/migen/build/platforms/sinara/sayma_amc.py b/migen/build/platforms/sinara/sayma_amc.py
@@ -15,6 +15,24 @@
         Subsignal("rx", Pins("AL8")),
         IOStandard("LVCMOS18")
     ),
+    ("serial", 1,
+        Subsignal("tx", Pins("M27")),
+        Subsignal("rx", Pins("L27")),
+        IOStandard("LVCMOS18")
+    ),
+    ("serial_rtm", 0,
+        Subsignal("tx", Pins("G27")),
+        Subsignal("rx", Pins("H27")),
+        IOStandard("LVCMOS18")
+    ),
+
+    # this is the second SPI flash (not containing the bitstream)
+    # clock is shared with the bitstream flash and needs to be accessed through STARTUPE3
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("K21")),
+        Subsignal("dq", Pins("M20 L20 R21 R22")),
+        IOStandard("LVCMOS25")
+    ),
 
     ("ddram_32", 1,
         Subsignal("a", Pins(