liteeth: clean up rgmii clocking

m-labs · Aug 20, 2017 · 1dd3a43 · 1dd3a43
1 parent 3ada03f
commit 1dd3a43
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/misoc/cores/liteeth_mini/phy/rgmii.py b/misoc/cores/liteeth_mini/phy/rgmii.py
@@ -36,11 +36,11 @@ def __init__(self, pads):
                                       ClockSignal("eth_rx"))
 
         rx_ctl_d = Signal()
-        self.sync += rx_ctl_d.eq(rx_ctl)
+        self.sync.eth_rx += rx_ctl_d.eq(rx_ctl)
         eop = Signal()
         self.comb += eop.eq(~rx_ctl & rx_ctl_d)
 
-        self.sync += [
+        self.sync.eth_rx += [
             source.stb.eq(rx_ctl),
             source.data.eq(rx_data)
         ]
@@ -75,6 +75,6 @@ class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads):
         self.dw = 8
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads)
-        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
-        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
+        self.submodules.tx = LiteEthPHYRGMIITX(pads)
+        self.submodules.rx = LiteEthPHYRGMIIRX(pads)
         self.sink, self.source = self.tx.sink, self.rx.source