Skip to content

Commit 25f9044

Browse files
committedAug 20, 2017
liteeth: clean up rgmii rx_ctl handling
1 parent bbcf121 commit 25f9044

File tree

1 file changed

+2
-5
lines changed

1 file changed

+2
-5
lines changed
 

Diff for: ‎misoc/cores/liteeth_mini/phy/rgmii.py

+2-5
Original file line numberDiff line numberDiff line change
@@ -36,15 +36,12 @@ def __init__(self, pads):
3636
ClockSignal("eth_rx"))
3737

3838
rx_ctl_d = Signal()
39-
self.sync.eth_rx += rx_ctl_d.eq(rx_ctl)
40-
eop = Signal()
41-
self.comb += eop.eq(~rx_ctl & rx_ctl_d)
42-
4339
self.sync.eth_rx += [
40+
rx_ctl_d.eq(rx_ctl),
4441
source.stb.eq(rx_ctl),
4542
source.data.eq(rx_data)
4643
]
47-
self.comb += source.eop.eq(eop)
44+
self.comb += source.eop.eq(~rx_ctl & rx_ctl_d)
4845

4946

5047
class LiteEthPHYRGMIICRG(Module, AutoCSR):

0 commit comments

Comments
 (0)
Please sign in to comment.