sayma_amc: fix FTDI UART I/O voltage

m-labs · Aug 20, 2017 · 0f78f9f · 0f78f9f
1 parent 26da349
commit 0f78f9f
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/migen/build/platforms/sinara/sayma_amc.py b/migen/build/platforms/sinara/sayma_amc.py
@@ -13,12 +13,12 @@
     ("serial", 0,
         Subsignal("tx", Pins("AK8")),
         Subsignal("rx", Pins("AL8")),
-        IOStandard("LVCMOS18")
+        IOStandard("LVCMOS33")
     ),
     ("serial", 1,
         Subsignal("tx", Pins("M27")),
         Subsignal("rx", Pins("L27")),
-        IOStandard("LVCMOS18")
+        IOStandard("LVCMOS33")
     ),
     ("serial_rtm", 0,
         Subsignal("tx", Pins("G27")),