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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 784ffb6a3fe8
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Aug 20, 2017

  1. sayma_amc: use standard MiSoC support for value-less config options

    @sbourdeauducq
    sbourdeauducq committed Aug 20, 2017
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    ee77c41 View commit details

  2. kc705: cleanup csr_devices

    @sbourdeauducq
    sbourdeauducq committed Aug 20, 2017
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    b6db9c2 View commit details

  3. sayma_amc: add spiflash

    @sbourdeauducq
    sbourdeauducq committed Aug 20, 2017
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    784ffb6 View commit details
Showing with 22 additions and 3 deletions.
  1. +2 −1 misoc/targets/kc705.py
  2. +20 −2 misoc/targets/sayma_amc.py
3 changes: 2 additions & 1 deletion misoc/targets/kc705.py
View file
Original file line number Diff line number Diff line change
@@ -78,14 +78,14 @@ def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
**kwargs)
self.csr_devices += ["spiflash", "ddrphy"]

self.submodules.crg = _CRG(platform)

self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
sdram_module = MT8JTF12864(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
self.csr_devices.append("ddrphy")

if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
@@ -98,6 +98,7 @@ def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus, 16*1024*1024)
self.csr_devices.append("spiflash")


class MiniSoC(BaseSoC):
22 changes: 20 additions & 2 deletions misoc/targets/sayma_amc.py
View file
Original file line number Diff line number Diff line change
@@ -8,6 +8,7 @@

from misoc.cores.sdram_settings import MT41J256M16
from misoc.cores.sdram_phy import kusddrphy
from misoc.cores import spi_flash
from misoc.cores.liteeth_mini.phy import LiteEthPHY
from misoc.cores.liteeth_mini.mac import LiteEthMAC
from misoc.integration.soc_sdram import *
@@ -76,15 +77,32 @@ def __init__(self, sdram="ddram_64", sdram_controller_type="minicon", **kwargs):
SoCSDRAM.__init__(self, platform, clk_freq=125*1000000,
integrated_rom_size=0x10000,
**kwargs)
self.csr_devices += ["ddrphy"]

self.submodules.crg = _CRG(platform)

self.submodules.ddrphy = kusddrphy.KUSDDRPHY(platform.request(sdram))
self.config["KUSDDRPHY"] = 1
self.config["KUSDDRPHY"] = None
sdram_module = MT41J256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_controller_type,
sdram_module.geom_settings, sdram_module.timing_settings)
self.csr_devices.append("ddrphy")

if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE3", i_GSR=0, i_GTS=0,
i_KEYCLEARB=0, i_PACK=1,
i_USRDONEO=1, i_USRDONETS=1,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0,
i_FCSBO=1, i_FCSBTS=0,
o_DI=di, i_DO=do, i_DTS=0b1110)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.config["SPIFLASH_PAGE_SIZE"] = 256
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x10000
self.register_rom(self.spiflash.bus, 16*1024*1024)
self.csr_devices.append("spiflash")


class MiniSoC(BaseSoC):
mem_map = {