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Added RedundantFF test
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azonenberg committed Aug 29, 2017
1 parent d826b1e commit 0201eb0
Showing 3 changed files with 87 additions and 11 deletions.
1 change: 1 addition & 0 deletions tests/greenpak4/slg46620v/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -12,6 +12,7 @@ add_greenpak4_bitstream(Inverters SLG46620V)
add_greenpak4_bitstream(Location SLG46620V Location.pcf)
add_greenpak4_bitstream(Loop SLG46620V)
add_greenpak4_bitstream(POR SLG46620V)
add_greenpak4_bitstream(RedundantFF SLG46620V)
add_greenpak4_bitstream(SPIToDCMP SLG46620V)
add_greenpak4_bitstream(Tristate SLG46620V)
add_greenpak4_bitstream(UART SLG46620V)
36 changes: 25 additions & 11 deletions tests/greenpak4/slg46620v/Counter.v
Original file line number Diff line number Diff line change
@@ -55,16 +55,30 @@ module Counter(rst, dout);
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// A counter with a pre-divider of 12

GP_COUNT8 #(
.RESET_MODE("LEVEL"),
.COUNT_TO(253),
.CLKIN_DIVIDE(1)
) cnt (
.CLK(clk_6khz_cnt),
.RST(rst),
.OUT(dout)
);
// A counter

localparam COUNT_MAX = 31;

//Fabric post-divider
reg[7:0] count = COUNT_MAX;
always @(posedge clk_6khz_cnt, posedge rst) begin

//level triggered reset
if(rst)
count <= 0;

//counter
else begin

if(count == 0)
count <= COUNT_MAX;
else
count <= count - 1'd1;

end

end

assign dout = (count == 0);

endmodule
61 changes: 61 additions & 0 deletions tests/greenpak4/slg46620v/RedundantFF.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
/***********************************************************************************************************************
* Copyright (C) 2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/

`default_nettype none

/**
A counter that includes redundant flipflops (the high 4 FFs never go high)
*/
module RedundantFF(clear, underflow);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations

(* LOC = "P19" *)
input wire clear;

(* LOC = "P20" *)
output wire underflow;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Clock source

wire clk_108hz;
GP_LFOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OUT_DIV(16)
) lfosc (
.PWRDN(1'b0),
.CLKOUT(clk_108hz)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The counter

reg[7:0] count = 15;

always @(posedge clk_108hz) begin
count <= count - 1'h1;
if(count == 0)
count <= 15;
end

assign underflow = (count == 0);

endmodule

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