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/*********************************************************************************************************************** | ||
* Copyright (C) 2017 Andrew Zonenberg and contributors * | ||
* * | ||
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General * | ||
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) * | ||
* any later version. * | ||
* * | ||
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied * | ||
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for * | ||
* more details. * | ||
* * | ||
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may * | ||
* find one here: * | ||
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt * | ||
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software * | ||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA * | ||
**********************************************************************************************************************/ | ||
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`default_nettype none | ||
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/** | ||
A counter that includes redundant flipflops (the high 4 FFs never go high) | ||
*/ | ||
module RedundantFF(clear, underflow); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// I/O declarations | ||
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(* LOC = "P19" *) | ||
input wire clear; | ||
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(* LOC = "P20" *) | ||
output wire underflow; | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// Clock source | ||
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wire clk_108hz; | ||
GP_LFOSC #( | ||
.PWRDN_EN(0), | ||
.AUTO_PWRDN(0), | ||
.OUT_DIV(16) | ||
) lfosc ( | ||
.PWRDN(1'b0), | ||
.CLKOUT(clk_108hz) | ||
); | ||
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// | ||
// The counter | ||
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reg[7:0] count = 15; | ||
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always @(posedge clk_108hz) begin | ||
count <= count - 1'h1; | ||
if(count == 0) | ||
count <= 15; | ||
end | ||
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assign underflow = (count == 0); | ||
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endmodule |