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Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're…
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… multi-edge-sensitive and getting confused.
azonenberg committed Aug 28, 2017
1 parent 393b18e commit c314586
Showing 1 changed file with 34 additions and 34 deletions.
68 changes: 34 additions & 34 deletions techlibs/greenpak4/cells_sim_digital.v
Original file line number Diff line number Diff line change
@@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin

if(KEEP) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end

else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end

end
end

"FALLING": begin
always @(posedge CLK, negedge RST) begin

//Resets
if(RST) begin
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end

end
end

"FALLING": begin
always @(posedge CLK, negedge RST) begin

if(KEEP) begin
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end

//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end

end
end

@@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
"RISING": begin
always @(posedge CLK, posedge RST) begin

//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end

//Main counter
if(KEEP) begin
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end

end
end

"FALLING": begin
always @(posedge CLK, negedge RST) begin

//Resets
if(RST) begin
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end

end
end

"FALLING": begin
always @(posedge CLK, negedge RST) begin

//Main counter
if(KEEP) begin
else if(KEEP) begin
end
else if(UP) begin
count <= count + 1'd1;
@@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
count <= COUNT_TO;
end

//Resets
if(!RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end

end
end

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