Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.

azonenberg · azonenberg · commit c3145863e7a8 · 2017-08-28T14:25:46.000-07:00
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
@@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
 
-					if(KEEP) begin
+					//Resets
+					if(RST) begin
+						if(RESET_VALUE == "ZERO")
+							count	<= 0;
+						else
+							count	<= COUNT_TO;
+					end
+
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
+				end
+			end
+
+			"FALLING": begin
+				always @(posedge CLK, negedge RST) begin
+
 					//Resets
-					if(RST) begin
+					if(!RST) begin
 						if(RESET_VALUE == "ZERO")
 							count	<= 0;
 						else
 							count	<= COUNT_TO;
 					end
 
-				end
-			end
-
-			"FALLING": begin
-				always @(posedge CLK, negedge RST) begin
-
-					if(KEEP) begin
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
-					//Resets
-					if(!RST) begin
-						if(RESET_VALUE == "ZERO")
-							count	<= 0;
-						else
-							count	<= COUNT_TO;
-					end
-
 				end
 			end
 
@@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
 
+					//Resets
+					if(RST) begin
+						if(RESET_VALUE == "ZERO")
+							count	<= 0;
+						else
+							count	<= COUNT_TO;
+					end
+
 					//Main counter
-					if(KEEP) begin
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
+				end
+			end
+
+			"FALLING": begin
+				always @(posedge CLK, negedge RST) begin
+
 					//Resets
-					if(RST) begin
+					if(!RST) begin
 						if(RESET_VALUE == "ZERO")
 							count	<= 0;
 						else
 							count	<= COUNT_TO;
 					end
 
-				end
-			end
-
-			"FALLING": begin
-				always @(posedge CLK, negedge RST) begin
-
 					//Main counter
-					if(KEEP) begin
+					else if(KEEP) begin
 					end
 					else if(UP) begin
 						count		<= count + 1'd1;
@@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 							count	<= COUNT_TO;
 					end
 
-					//Resets
-					if(!RST) begin
-						if(RESET_VALUE == "ZERO")
-							count	<= 0;
-						else
-							count	<= COUNT_TO;
-					end
-
 				end
 			end
 
