extract_reduce: Fix segfault on "undriven" inputs

ArcaneNibble · azonenberg · commit ab1bf8d661d3 · 2017-09-14T12:54:44.000-07:00
This is easily triggered when un-techmapping if the technology-specific
cell library isn't loaded. Outputs of technology-specific cells will be
seen as inputs, and nets using those outputs will be seen as undriven.
Just ignore these cells because they can't be part of a reduce chain
anyways.
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
@@ -160,7 +160,7 @@ struct ExtractReducePass : public Pass
 					if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
 					{
 						Cell* cell_a = sig_to_driver[a[0]];
-						if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
+						if (cell_a && ((cell_a->type == "$_AND_" && gt == GateType::And) ||
 							(cell_a->type == "$_OR_" && gt == GateType::Or) ||
 							(cell_a->type == "$_XOR_" && gt == GateType::Xor)))
 						{
@@ -177,7 +177,7 @@ struct ExtractReducePass : public Pass
 					if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
 					{
 						Cell* cell_b = sig_to_driver[b[0]];
-						if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
+						if (cell_b && ((cell_b->type == "$_AND_" && gt == GateType::And) ||
 							(cell_b->type == "$_OR_" && gt == GateType::Or) ||
 							(cell_b->type == "$_XOR_" && gt == GateType::Xor)))
 						{

Original file line number	Diff line number	Diff line change
`@@ -160,7 +160,7 @@ struct ExtractReducePass : public Pass`
`160`	`160`	`if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)`
`161`	`161`	`{`
`162`	`162`	`Cell* cell_a = sig_to_driver[a[0]];`
`163`		`- if (((cell_a->type == "$_AND_" && gt == GateType::And) \|\|`
	`163`	`+ if (cell_a && ((cell_a->type == "$_AND_" && gt == GateType::And) \|\|`
`164`	`164`	`(cell_a->type == "$_OR_" && gt == GateType::Or) \|\|`
`165`	`165`	`(cell_a->type == "$_XOR_" && gt == GateType::Xor)))`
`166`	`166`	`{`
`@@ -177,7 +177,7 @@ struct ExtractReducePass : public Pass`
`177`	`177`	`if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)`
`178`	`178`	`{`
`179`	`179`	`Cell* cell_b = sig_to_driver[b[0]];`
`180`		`- if (((cell_b->type == "$_AND_" && gt == GateType::And) \|\|`
	`180`	`+ if (cell_b && ((cell_b->type == "$_AND_" && gt == GateType::And) \|\|`
`181`	`181`	`(cell_b->type == "$_OR_" && gt == GateType::Or) \|\|`
`182`	`182`	`(cell_b->type == "$_XOR_" && gt == GateType::Xor)))`
`183`	`183`	`{`