m-labs · Aug 26, 2017 · Aug 26, 2017 · Aug 26, 2017
Showing with 14 additions and 2 deletions.

+1 −1 misoc/integration/cpu_interface.py

+12 −0 misoc/interconnect/csr.py

+1 −1 misoc/interconnect/wishbone.py
diff --git a/misoc/integration/cpu_interface.py b/misoc/integration/cpu_interface.py
@@ -295,6 +295,6 @@ def get_csr_csv(regions):
         if not isinstance(obj, Memory):
             for csr in obj:
                 nr = (csr.size + busword - 1)//busword
-                r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if is_readonly(csr) else "rw")
+                r += "{}.{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if is_readonly(csr) else "rw")
                 origin += 4*nr
     return r
diff --git a/misoc/interconnect/csr.py b/misoc/interconnect/csr.py
@@ -56,6 +56,9 @@ def read(self):
         """Read method for simulation."""
         return self.value.value
 
+    def __str__(self):
+        return "<CSRConstant {}>".format(self.name)
+
 
 class CSR(_CSRBase):
     """Basic CSR register.
@@ -101,6 +104,9 @@ def write(self, value):
         yield
         yield self.re.eq(0)
 
+    def __str__(self):
+        return "<CSR {}({})>".format(self.name, self.size)
+
 
 class _CompoundCSR(_CSRBase, Module):
     def __init__(self, size, name):
@@ -166,6 +172,9 @@ def read(self):
         """Read method for simulation."""
         return (yield self.status)
 
+    def __str__(self):
+        return "<CSRStatus {}({})>".format(self.name, self.size)
+
 
 class CSRStorage(_CompoundCSR):
     """Control Register.
@@ -273,6 +282,9 @@ def write(self, value):
         yield
         yield self.re.eq(0)
 
+    def __str__(self):
+        return "<CSRStorage {}({})>".format(self.name, self.size)
+
 
 def csrprefix(prefix, csrs, done):
     for csr in csrs:

diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
@@ -647,7 +647,7 @@ def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
         # generate ack
         self.sync += [
             self.bus.ack.eq(0),
-            If(self.bus.cyc & self.bus.stb & ~self.bus.ack,    self.bus.ack.eq(1))
+            If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
         ]