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base repository: m-labs/migen
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Aug 26, 2017

  1. sayma_rtm: add clock mux pins

    @sbourdeauducq
    sbourdeauducq committed Aug 26, 2017
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    185c3c6 View commit details

  2. sayma_rtm: add DAC pins

    @sbourdeauducq
    sbourdeauducq committed Aug 26, 2017
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    e745f7c View commit details
Showing with 24 additions and 0 deletions.
  1. +24 −0 migen/build/platforms/sinara/sayma_rtm.py
24 changes: 24 additions & 0 deletions migen/build/platforms/sinara/sayma_rtm.py
View file
Original file line number Diff line number Diff line change
@@ -31,6 +31,30 @@
IOStandard("LVCMOS25")
),
("hmc7043_reset", 0, Pins("E17"), IOStandard("LVCMOS25")),

# clock mux
("clk_src_ext_sel", 0, Pins("P15"), IOStandard("LVCMOS25")),
("ref_clk_src_sel", 0, Pins("J14"), IOStandard("LVCMOS25")),
("dac_clk_src_sel", 0, Pins("P16"), IOStandard("LVCMOS25")),

# DACs
("ad9154_rst_n", 0, Pins("U15"), IOStandard("LVCMOS25")),
("ad9154_spi", 0,
Subsignal("clk", Pins("T13")),
Subsignal("cs_n", Pins("U14")),
Subsignal("mosi", Pins("V17")),
Subsignal("miso", Pins("R13")),
IOStandard("LVCMOS25")
),
("ad9154_txen", 0, Pins("V16 U16"), IOStandard("LVCMOS25")),
("ad9154_spi", 1,
Subsignal("clk", Pins("J15")),
Subsignal("cs_n", Pins("K18")),
Subsignal("mosi", Pins("J18")),
Subsignal("miso", Pins("J16")),
IOStandard("LVCMOS25")
),
("ad9154_txen", 1, Pins("L17 L14"), IOStandard("LVCMOS25")),
]