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base repository: azonenberg/yosys
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Sep 11, 2017

  1. Cleaned up some dead code

    @azonenberg
    azonenberg committed Sep 11, 2017
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    4d07f4c View commit details

  2. Merge branch 'master' of github.com:azonenberg/yosys

    @azonenberg
    azonenberg committed Sep 11, 2017
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    29edbc9 View commit details
Showing with 0 additions and 265 deletions.
  1. +0 −265 passes/techmap/extract_bus.cc
265 changes: 0 additions & 265 deletions passes/techmap/extract_bus.cc
View file
Original file line number Diff line number Diff line change
@@ -24,271 +24,6 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

/*
//get the list of cells hooked up to at least one bit of a given net
pool<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
{
pool<Cell*> rval;
for(auto b : port)
{
pool<ModIndex::PortInfo> ports = index.query_ports(b);
for(auto x : ports)
{
if(x.cell == src)
continue;
rval.insert(x.cell);
}
}
return rval;
}
//return true if there is a full-width bus connection from cell a port ap to cell b port bp
//if other_conns_allowed is false, then we require a strict point to point connection (no other links)
bool is_full_bus(
const RTLIL::SigSpec& sig,
ModIndex& index,
Cell* a,
RTLIL::IdString ap,
Cell* b,
RTLIL::IdString bp,
bool other_conns_allowed = false)
{
for(auto s : sig)
{
pool<ModIndex::PortInfo> ports = index.query_ports(s);
bool found_a = false;
bool found_b = false;
for(auto x : ports)
{
if( (x.cell == a) && (x.port == ap) )
found_a = true;
else if( (x.cell == b) && (x.port == bp) )
found_b = true;
else if(!other_conns_allowed)
return false;
}
if( (!found_a) || (!found_b) )
return false;
}
return true;
}
//return true if the signal connects to one port only (nothing on the other end)
bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
{
for(auto b : port)
{
pool<ModIndex::PortInfo> ports = index.query_ports(b);
if(ports.size() > 1)
return false;
}
return true;
}
struct CounterExtraction
{
int width; //counter width
RTLIL::Wire* rwire; //the register output
bool has_reset; //true if we have a reset
RTLIL::SigSpec rst; //reset pin
int count_value; //value we count from
RTLIL::SigSpec clk; //clock signal
RTLIL::SigSpec outsig; //counter output signal
RTLIL::Cell* count_mux; //counter mux
RTLIL::Cell* count_reg; //counter register
RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
pool<ModIndex::PortInfo> pouts; //Ports that take a parallel output from us
};
*/
/*
//attempt to extract a counter centered on the given adder cell
//For now we only support DOWN counters.
//TODO: up/down support
int bus_tryextract(
ModIndex& index,
Cell *cell,
CounterExtraction& extract,
pool<RTLIL::IdString>& parallel_cells,
int maxwidth)
{
SigMap& sigmap = index.sigmap;
//A counter with less than 2 bits makes no sense
//TODO: configurable min threshold
int a_width = cell->getParam("\\A_WIDTH").as_int();
extract.width = a_width;
if( (a_width < 2) || (a_width > maxwidth) )
return 1;
//Second input must be a single bit
int b_width = cell->getParam("\\B_WIDTH").as_int();
if(b_width != 1)
return 2;
//Both inputs must be unsigned, so don't extract anything with a signed input
bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
if(a_sign || b_sign)
return 3;
//To be a counter, one input of the ALU must be a constant 1
//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
return 4;
//BI and CI must be constant 1 as well
const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
return 5;
const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
return 6;
//CO and X must be unconnected (exactly one connection to each port)
if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
return 7;
if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
return 8;
//Y must have exactly one connection, and it has to be a $mux cell.
//We must have a direct bus connection from our Y to their A.
const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
if(y_loads.size() != 1)
return 9;
Cell* count_mux = *y_loads.begin();
extract.count_mux = count_mux;
if(count_mux->type != "$mux")
return 10;
if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
return 11;
//B connection of the mux is our underflow value
const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B"));
if(!underflow.is_fully_const())
return 12;
extract.count_value = underflow.as_int();
//S connection of the mux must come from an inverter (need not be the only load)
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
extract.outsig = muxsel;
pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
Cell* underflow_inv = NULL;
for(auto c : muxsel_conns)
{
if(c->type != "$logic_not")
continue;
if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
continue;
underflow_inv = c;
break;
}
if(underflow_inv == NULL)
return 13;
extract.underflow_inv = underflow_inv;
//Y connection of the mux must have exactly one load, the counter's internal register
const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
if(muxy_loads.size() != 1)
return 14;
Cell* count_reg = *muxy_loads.begin();
extract.count_reg = count_reg;
if(count_reg->type == "$dff")
extract.has_reset = false;
else if(count_reg->type == "$adff")
{
extract.has_reset = true;
//Verify ARST_VALUE is zero and ARST_POLARITY is 1
//TODO: infer an inverter to make it 1 if necessary, so we can support negative level resets?
if(count_reg->getParam("\\ARST_POLARITY").as_int() != 1)
return 22;
if(count_reg->getParam("\\ARST_VALUE").as_int() != 0)
return 23;
//Save the reset
extract.rst = sigmap(count_reg->getPort("\\ARST"));
}
//TODO: support synchronous reset
else
return 15;
if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
return 16;
//TODO: Verify count_reg CLK_POLARITY is 1
//Register output must have exactly two loads, the inverter and ALU
//(unless we have a parallel output!)
const RTLIL::SigSpec qport = count_reg->getPort("\\Q");
const RTLIL::SigSpec cnout = sigmap(qport);
pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
if(cnout_loads.size() > 2)
{
//If we specified a limited set of cells for parallel output, check that we only drive them
if(!parallel_cells.empty())
{
for(auto c : cnout_loads)
{
if(c == underflow_inv)
continue;
if(c == cell)
continue;
//Make sure we're in the whitelist
if( parallel_cells.find(c->type) == parallel_cells.end())
return 17;
//Figure out what port(s) are driven by it
//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
RTLIL::IdString portname;
for(auto b : qport)
{
pool<ModIndex::PortInfo> ports = index.query_ports(b);
for(auto x : ports)
{
if(x.cell != c)
continue;
if(portname == "")
portname = x.port;
//somehow our counter output is going to multiple ports
//this makes no sense, don't allow inference
else if(portname != x.port)
return 17;
}
}
//Save the other loads
extract.pouts.insert(ModIndex::PortInfo(c, portname, 0));
}
}
}
if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
return 18;
if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
return 19;
//Look up the clock from the register
extract.clk = sigmap(count_reg->getPort("\\CLK"));
//Register output net must have an INIT attribute equal to the count value
extract.rwire = cnout.as_wire();
if(extract.rwire->attributes.find("\\init") == extract.rwire->attributes.end())
return 20;
int rinit = extract.rwire->attributes["\\init"].as_int();
if(rinit != extract.count_value)
return 21;
return 0;
}
*/

void bus_worker(
ModIndex& index,
Cell *cell,