hdl/csc: add latency parameter and some cleanup

timvideos · Aug 11, 2015 · 8c238f5 · 8c238f5
1 parent afa42db
commit 8c238f5
Show file tree

Hide file tree

Showing 4 changed files with 4 additions and 9 deletions.
diff --git a/hdl/csc/rgb2ycbcr.py b/hdl/csc/rgb2ycbcr.py
@@ -8,9 +8,6 @@
 
 # TODO:
 # - see if we can regroup some stages without impacting timings (would reduce latency and registers).
-# - test implementation
-# - do more tests.
-
 
 def rgb2ycbcr_coefs(dw, cw=None):
     return {
@@ -137,6 +134,7 @@ def __init__(self, rgb_w=8, ycbcr_w=8, coef_w=8):
         self.sink = sink = Sink(EndpointDescription(rgb_layout(rgb_w), packetized=True))
         self.source = source = Source(EndpointDescription(ycbcr_layout(ycbcr_w), packetized=True))
         PipelinedActor.__init__(self, datapath_latency)
+        self.latency = datapath_latency
 
         # # #
 

diff --git a/hdl/csc/ycbcr2rgb.py b/hdl/csc/ycbcr2rgb.py
@@ -6,10 +6,6 @@
 
 from hdl.csc.common import *
 
-# TODO:
-# - test implementation
-# - do more test
-
 def ycbcr2rgb_coefs(dw, cw=None):
     ca = 0.1819
     cb = 0.0618
@@ -113,6 +109,7 @@ def __init__(self, ycbcr_w=8, rgb_w=8, coef_w=8):
         self.sink = sink = Sink(EndpointDescription(ycbcr_layout(ycbcr_w), packetized=True))
         self.source = source = Source(EndpointDescription(rgb_layout(rgb_w), packetized=True))
         PipelinedActor.__init__(self, datapath_latency)
+        self.latency = datapath_latency
 
         # # #
 

diff --git a/hdl/dvisampler/analysis.py b/hdl/dvisampler/analysis.py
@@ -139,7 +139,7 @@ def __init__(self, word_width, fifo_depth):
         ]
         de = self.de
         vsync = self.vsync
-        for i in range(8): # rgb2ycbcr latency
+        for i in range(rgb2ycbcr.latency):
             next_de = Signal()
             next_vsync = Signal()
             self.sync.pix += [

diff --git a/hdl/framebuffer/phy.py b/hdl/framebuffer/phy.py
@@ -214,7 +214,7 @@ def __init__(self, pack_factor, pads_vga, pads_dvi):
         de = fifo.pix_de
         hsync = fifo.pix_hsync
         vsync = fifo.pix_vsync
-        for i in range(4): # ycbcr2rgb latency
+        for i in range(ycbcr2rgb.latency):
             next_de = Signal()
             next_vsync = Signal()
             next_hsync = Signal()