cores/liteeth_mini: continue cleanup - use layout instead of descript…

…ion - use fifo depth of 64 for all phys
m-labs · Mar 6, 2016 · 90e1d09 · 90e1d09
1 parent 58510dd
commit 90e1d09
Showing 13 changed files with 84 additions and 89 deletions.
diff --git a/misoc/cores/liteeth_mini/common.py b/misoc/cores/liteeth_mini/common.py
@@ -7,14 +7,14 @@
 buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
 
 
-def eth_phy_description(dw):
+def eth_phy_layout(dw):
     return [
         ("data", dw),
         ("last_be", dw//8),
         ("error", dw//8)
     ]
 
-def eth_mac_description(dw):
+def eth_mac_layout(dw):
     return mac_header.get_layout() + [
         ("data", dw),
         ("last_be", dw//8),

diff --git a/misoc/cores/liteeth_mini/mac/core.py b/misoc/cores/liteeth_mini/mac/core.py
@@ -4,7 +4,6 @@
 from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import *
 from misoc.cores.liteeth_mini.mac import gap, preamble, crc, padding, last_be
-from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
 
 
 class LiteEthMACCore(Module, AutoCSR):
@@ -36,8 +35,8 @@ def __init__(self, phy, dw, endianness="big",
             self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
 
             # CRC insert/check
-            crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
-            crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
+            crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_layout(phy.dw))
+            crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_layout(phy.dw))
             self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
             self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)
 
@@ -67,11 +66,11 @@ def __init__(self, phy, dw, endianness="big",
         # Converters
         if dw != phy.dw:
             reverse = endianness == "big"
-            tx_converter = stream.Converter(eth_phy_description(dw),
-                                     eth_phy_description(phy.dw),
+            tx_converter = stream.Converter(eth_phy_layout(dw),
+                                     eth_phy_layout(phy.dw),
                                      reverse=reverse)
-            rx_converter = stream.Converter(eth_phy_description(phy.dw),
-                                     eth_phy_description(dw),
+            rx_converter = stream.Converter(eth_phy_layout(phy.dw),
+                                     eth_phy_layout(dw),
                                      reverse=reverse)
             self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
             self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
@@ -80,12 +79,8 @@ def __init__(self, phy, dw, endianness="big",
             rx_pipeline += [rx_converter]
 
         # Cross Domain Crossing
-        if isinstance(phy, LiteEthPHYMII):
-            fifo_depth = 8
-        else:
-            fifo_depth = 64
-        tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
-        rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
+        tx_cdc = stream.AsyncFIFO(eth_phy_layout(dw), 64)
+        rx_cdc = stream.AsyncFIFO(eth_phy_layout(dw), 64)
         self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
         self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
 

diff --git a/misoc/cores/liteeth_mini/mac/crc.py b/misoc/cores/liteeth_mini/mac/crc.py
@@ -128,8 +128,8 @@ class LiteEthMACCRCInserter(Module):
 
     Parameters
     ----------
-    description : description
-        description of the dataflow.
+    layout : layout
+        layout of the dataflow.
 
     Attributes
     ----------
@@ -138,9 +138,9 @@ class LiteEthMACCRCInserter(Module):
     source : out
         Packets output with CRC.
     """
-    def __init__(self, crc_class, description):
-        self.sink = sink = stream.Endpoint(description)
-        self.source = source = stream.Endpoint(description)
+    def __init__(self, crc_class, layout):
+        self.sink = sink = stream.Endpoint(layout)
+        self.source = source = stream.Endpoint(layout)
 
         # # #
 
@@ -195,8 +195,8 @@ def __init__(self, crc_class, description):
 
 
 class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
-    def __init__(self, description):
-        LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description)
+    def __init__(self, layout):
+        LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, layout)
 
 
 class LiteEthMACCRCChecker(Module):
@@ -206,8 +206,8 @@ class LiteEthMACCRCChecker(Module):
 
     Parameters
     ----------
-    description : description
-        description of the dataflow.
+    layout : layout
+        layout of the dataflow.
 
     Attributes
     ----------
@@ -217,9 +217,9 @@ class LiteEthMACCRCChecker(Module):
         Packets output without CRC and "error" set to 0
         on eop when CRC OK / set to 1 when CRC KO.
     """
-    def __init__(self, crc_class, description):
-        self.sink = sink = stream.Endpoint(description)
-        self.source = source = stream.Endpoint(description)
+    def __init__(self, crc_class, layout):
+        self.sink = sink = stream.Endpoint(layout)
+        self.source = source = stream.Endpoint(layout)
 
         # # #
 
@@ -228,7 +228,7 @@ def __init__(self, crc_class, description):
         self.submodules += crc
         ratio = crc.width//dw
 
-        fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
+        fifo = ResetInserter()(stream.SyncFIFO(layout, ratio + 1))
         self.submodules += fifo
 
         fsm = FSM(reset_state="RESET")
@@ -278,5 +278,5 @@ def __init__(self, crc_class, description):
 
 
 class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
-    def __init__(self, description):
-        LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description)
+    def __init__(self, layout):
+        LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, layout)
diff --git a/misoc/cores/liteeth_mini/mac/gap.py b/misoc/cores/liteeth_mini/mac/gap.py
@@ -4,13 +4,13 @@
 from migen.genlib.fsm import *
 
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
+from misoc.cores.liteeth_mini.common import eth_phy_layout, eth_interpacket_gap
 
 
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):
-        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/last_be.py b/misoc/cores/liteeth_mini/mac/last_be.py
@@ -1,13 +1,13 @@
 from migen import *
 
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_description
+from misoc.cores.liteeth_mini.common import eth_phy_layout
 
 
 class LiteEthMACTXLastBE(Module):
     def __init__(self, dw):
-        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 
@@ -30,15 +30,12 @@ def __init__(self, dw):
 
 class LiteEthMACRXLastBE(Module):
     def __init__(self, dw):
-        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 
         self.comb += [
-            source.stb.eq(sink.stb),
-            source.eop.eq(sink.eop),
-            source.data.eq(sink.data),
-            source.last_be.eq(sink.eop),
-            sink.ack.eq(source.ack)
+            sink.connect(source),
+            source.last_be.eq(sink.eop)
         ]
diff --git a/misoc/cores/liteeth_mini/mac/padding.py b/misoc/cores/liteeth_mini/mac/padding.py
@@ -3,13 +3,13 @@
 from migen import *
 
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_description
+from misoc.cores.liteeth_mini.common import eth_phy_layout
 
 
 class LiteEthMACPaddingInserter(Module):
     def __init__(self, dw, padding):
-        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 
@@ -19,11 +19,12 @@ def __init__(self, dw, padding):
         counter_done = Signal()
         counter_reset = Signal()
         counter_ce = Signal()
-        self.sync += If(counter_reset,
-                            counter.eq(0)
-                        ).Elif(counter_ce,
-                            counter.eq(counter + 1)
-                        )
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 1)
+            )
         self.comb += counter_done.eq(counter >= padding_limit)
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@@ -57,8 +58,8 @@ def __init__(self, dw, padding):
 
 class LiteEthMACPaddingChecker(Module):
     def __init__(self, dw, packet_min_length):
-        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/preamble.py b/misoc/cores/liteeth_mini/mac/preamble.py
@@ -4,13 +4,13 @@
 from migen.genlib.record import Record
 
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
+from misoc.cores.liteeth_mini.common import eth_phy_layout, eth_preamble
 
 
 class LiteEthMACPreambleInserter(Module):
     def __init__(self, dw):
-        self.sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 
@@ -62,8 +62,8 @@ def __init__(self, dw):
 
 class LiteEthMACPreambleChecker(Module):
     def __init__(self, dw):
-        self.sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = stream.Endpoint(eth_phy_layout(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/sram.py b/misoc/cores/liteeth_mini/mac/sram.py
@@ -3,12 +3,12 @@
 from misoc.interconnect.csr import *
 from misoc.interconnect.csr_eventmanager import *
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_description
+from misoc.cores.liteeth_mini.common import eth_phy_layout
 
 
 class LiteEthMACSRAMWriter(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2):
-        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(dw))
         self.crc_error = Signal()
 
         slotbits = max(log2_int(nslots), 1)
@@ -41,11 +41,12 @@ def __init__(self, dw, depth, nslots=2):
         counter = Signal(lengthbits)
         counter_reset = Signal()
         counter_ce = Signal()
-        self.sync += If(counter_reset,
-                        counter.eq(0)
-                    ).Elif(counter_ce,
-                        counter.eq(counter + increment)
-                    )
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + increment)
+            )
 
         # slot computation
         slot = Signal(slotbits)
@@ -126,7 +127,7 @@ def __init__(self, dw, depth, nslots=2):
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2):
-        self.source = source = stream.Endpoint(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         slotbits = max(log2_int(nslots), 1)
         lengthbits = log2_int(depth*4)  # length in bytes
@@ -157,11 +158,12 @@ def __init__(self, dw, depth, nslots=2):
         counter = Signal(lengthbits)
         counter_reset = Signal()
         counter_ce = Signal()
-        self.sync += If(counter_reset,
-                            counter.eq(0)
-                        ).Elif(counter_ce,
-                            counter.eq(counter + 4)
-                        )
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 4)
+            )
 
 
         # fsm

diff --git a/misoc/cores/liteeth_mini/mac/wishbone.py b/misoc/cores/liteeth_mini/mac/wishbone.py
@@ -4,14 +4,14 @@
 from misoc.interconnect import wishbone
 from misoc.interconnect.csr import *
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
+from misoc.cores.liteeth_mini.common import eth_phy_layout, buffer_depth
 from misoc.cores.liteeth_mini.mac import sram
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
     def __init__(self, dw, nrxslots=2, ntxslots=2):
-        self.sink = stream.Endpoint(eth_phy_description(dw))
-        self.source = stream.Endpoint(eth_phy_description(dw))
+        self.sink = stream.Endpoint(eth_phy_layout(dw))
+        self.source = stream.Endpoint(eth_phy_layout(dw))
         self.bus = wishbone.Interface()
 
         # # #

diff --git a/misoc/cores/liteeth_mini/phy/gmii.py b/misoc/cores/liteeth_mini/phy/gmii.py
@@ -9,7 +9,7 @@
 
 class LiteEthPHYGMIITX(Module):
     def __init__(self, pads):
-        self.sink = sink = stream.Endpoint(eth_phy_description(8))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
@@ -24,7 +24,7 @@ def __init__(self, pads):
 
 class LiteEthPHYGMIIRX(Module):
     def __init__(self, pads):
-        self.source = source = stream.Endpoint(eth_phy_description(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/phy/gmii_mii.py b/misoc/cores/liteeth_mini/phy/gmii_mii.py
@@ -21,7 +21,7 @@
 
 class LiteEthPHYGMIIMIITX(Module):
     def __init__(self, pads, mode):
-        self.sink = sink = stream.Endpoint(eth_phy_description(8))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
@@ -33,7 +33,7 @@ def __init__(self, pads, mode):
         mii_tx = LiteEthPHYMIITX(mii_tx_pads)
         self.submodules += mii_tx
 
-        demux = stream.Demultiplexer(eth_phy_description(8), 2)
+        demux = stream.Demultiplexer(eth_phy_layout(8), 2)
         self.submodules += demux
         self.comb += [
             demux.sel.eq(mode == modes["MII"]),
@@ -57,7 +57,7 @@ def __init__(self, pads, mode):
 
 class LiteEthPHYGMIIMIIRX(Module):
     def __init__(self, pads, mode):
-        self.source = source = stream.Endpoint(eth_phy_description(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
@@ -73,7 +73,7 @@ def __init__(self, pads, mode):
         mii_rx = LiteEthPHYMIIRX(pads_d)
         self.submodules += mii_rx
 
-        mux = stream.Multiplexer(eth_phy_description(8), 2)
+        mux = stream.Multiplexer(eth_phy_layout(8), 2)
         self.submodules += mux
         self.comb += [
             mux.sel.eq(mode == modes["MII"]),

diff --git a/misoc/cores/liteeth_mini/phy/mii.py b/misoc/cores/liteeth_mini/phy/mii.py
@@ -6,20 +6,20 @@
 from misoc.cores.liteeth_mini.common import *
 
 
-def converter_description(dw):
+def converter_layout(dw):
     return [("data", dw)]
 
 
 class LiteEthPHYMIITX(Module):
     def __init__(self, pads):
-        self.sink = sink = stream.Endpoint(eth_phy_description(8))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
         if hasattr(pads, "tx_er"):
             self.sync += pads.tx_er.eq(0)
-        converter = stream.Converter(converter_description(8),
-                              converter_description(4))
+        converter = stream.Converter(converter_layout(8),
+                              converter_layout(4))
         self.submodules += converter
         self.comb += [
             converter.sink.stb.eq(sink.stb),
@@ -35,12 +35,12 @@ def __init__(self, pads):
 
 class LiteEthPHYMIIRX(Module):
     def __init__(self, pads):
-        self.source = source = stream.Endpoint(eth_phy_description(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
-        converter = stream.Converter(converter_description(4),
-                              converter_description(8))
+        converter = stream.Converter(converter_layout(4),
+                              converter_layout(8))
         converter = ResetInserter()(converter)
         self.submodules += converter
 

diff --git a/misoc/cores/liteeth_mini/phy/s6rgmii.py b/misoc/cores/liteeth_mini/phy/s6rgmii.py
@@ -12,7 +12,7 @@
 
 class LiteEthPHYRGMIITX(Module):
     def __init__(self, pads):
-        self.sink = sink = stream.Endpoint(eth_phy_description(8))
+        self.sink = sink = stream.Endpoint(eth_phy_layout(8))
 
         # # #
 
@@ -34,7 +34,7 @@ def __init__(self, pads):
 
 class LiteEthPHYRGMIIRX(Module):
     def __init__(self, pads):
-        self.source = source = stream.Endpoint(eth_phy_description(8))
+        self.source = source = stream.Endpoint(eth_phy_layout(8))
 
         # # #