m-labs · Feb 29, 2016 · Feb 29, 2016 · Feb 29, 2016
Showing with 19 additions and 21 deletions.

+16 −18 artiq/gateware/spi.py

+1 −1 artiq/gateware/targets/kc705.py

+1 −1 artiq/gateware/targets/pipistrello.py

+1 −1 artiq/runtime/spi.c
diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py
@@ -282,10 +282,9 @@ def __init__(self, pads, bus=None, data_width=32):
         ])
         assert len(xfer) <= len(bus.dat_w)
 
-        # SPI
-        spi = SPIMachine(data_width, clock_width=len(config.div_read),
-                         bits_width=len(xfer.read_length))
-        self.submodules += spi
+        self.submodules.spi = spi = SPIMachine(
+            data_width, clock_width=len(config.div_read),
+            bits_width=len(xfer.read_length))
 
         wb_we = Signal()
         pending = Signal()
@@ -344,12 +343,12 @@ def __init__(self, pads, bus=None, data_width=32):
 
         self.comb += [
             clk_t.oe.eq(~config.offline),
+            clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
             mosi_t.oe.eq(~config.offline & spi.cs &
                          (spi.oe | ~config.half_duplex)),
-            clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
+            mosi_t.o.eq(spi.reg.o),
             spi.reg.i.eq(Mux(config.half_duplex, mosi_t.i,
                              getattr(pads, "miso", mosi_t.i))),
-            mosi_t.o.eq(spi.reg.o),
         ]
 
 
@@ -438,32 +437,31 @@ def _test_gen(bus):
                   hex(wdata), hex(rdata), hex(a), hex(b))
 
 
-
 class _TestPads:
     def __init__(self):
-        self.cs_n = Signal(3)
+        self.cs_n = Signal(2)
         self.clk = Signal()
         self.mosi = Signal()
         self.miso = Signal()
 
 
+class _TestTristate(Module):
+    def __init__(self, t):
+        oe = Signal()
+        self.comb += [
+            t.target.eq(t.o),
+            oe.eq(t.oe),
+            t.i.eq(t.o),
+        ]
+
 if __name__ == "__main__":
     from migen.fhdl.specials import Tristate
 
-    class T(Module):
-        def __init__(self, t):
-            oe = Signal()
-            self.comb += [
-                t.target.eq(t.o),
-                oe.eq(t.oe),
-                t.i.eq(t.o),
-            ]
-    Tristate.lower = staticmethod(lambda dr: T(dr))
-
     pads = _TestPads()
     dut = SPIMaster(pads)
     dut.comb += pads.miso.eq(pads.mosi)
     # from migen.fhdl.verilog import convert
     # print(convert(dut))
 
+    Tristate.lower = _TestTristate
     run_simulation(dut, _test_gen(dut.bus), vcd_name="spi_master.vcd")
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -259,7 +259,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
 
         phy = spi.SPIMaster(spi_pins)
         self.submodules += phy
-        self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
+        self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 

diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
@@ -200,7 +200,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
         spi_pins.cs_n = pmod.d[3:]
         phy = spi.SPIMaster(spi_pins)
         self.submodules += phy
-        self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
+        self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 

diff --git a/artiq/runtime/spi.c b/artiq/runtime/spi.c
@@ -12,7 +12,7 @@
 void spi_write(long long int timestamp, int channel, int addr,
         unsigned int data)
 {
-    rtio_chan_sel_write(CONFIG_RTIO_SPI_CHANNEL + channel);
+    rtio_chan_sel_write(channel);
     rtio_o_address_write(addr);
     rtio_o_data_write(data);
     rtio_o_timestamp_write(timestamp);