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jordensjordens
committedFeb 29, 2016
Merge branch 'master' into spimaster
* master: artiq_flash: use term 'gateware' targets/kc705-nist_clock: add clock generator on LA32 for testing purposes doc: insist that output() must be called on TTLInOut. Closes #297 doc: update install instructions coredevice: do not give up on UTF-8 errors in log. Closes #300 use m-labs setup for defaults fix indentation
·
8.01.0rc1
2 parents 6c899e6 + 6dd1eb2 commit 7ab7f7d

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‎artiq/coredevice/comm_generic.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,7 @@ def _read_bytes(self):
158158
return self._read_chunk(self._read_int32())
159159

160160
def _read_string(self):
161-
return self._read_bytes()[:-1].decode('utf-8')
161+
return self._read_bytes()[:-1].decode("utf-8")
162162

163163
#
164164
# Writer interface
@@ -242,7 +242,7 @@ def get_log(self):
242242

243243
self._read_header()
244244
self._read_expect(_D2HMsgType.LOG_REPLY)
245-
return self._read_chunk(self._read_length).decode("utf-8")
245+
return self._read_chunk(self._read_length).decode("utf-8", "replace")
246246

247247
def clear_log(self):
248248
self._write_empty(_H2DMsgType.LOG_CLEAR)

‎artiq/coredevice/ttl.py

+13-2
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,11 @@ class TTLInOut:
9191
9292
This should be used with bidirectional channels.
9393
94+
Note that the channel is in input mode by default. If you need to drive a
95+
signal, you must call ``output``. If the channel is in output mode most of
96+
the time in your setup, it is a good idea to call ``output`` in the
97+
startup kernel.
98+
9499
:param channel: channel number
95100
"""
96101
def __init__(self, dmgr, channel):
@@ -107,12 +112,18 @@ def set_oe(self, oe):
107112

108113
@kernel
109114
def output(self):
110-
"""Set the direction to output."""
115+
"""Set the direction to output.
116+
117+
There must be a delay of at least one RTIO clock cycle before any
118+
other command can be issued."""
111119
self.set_oe(True)
112120

113121
@kernel
114122
def input(self):
115-
"""Set the direction to input."""
123+
"""Set the direction to input.
124+
125+
There must be a delay of at least one RTIO clock cycle before any
126+
other command can be issued."""
116127
self.set_oe(False)
117128

118129
@kernel

‎artiq/frontend/artiq_flash.py

+12-13
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@
66
import subprocess
77
import tempfile
88

9-
import artiq
109
from artiq import __artiq_dir__ as artiq_dir
1110
from artiq.frontend.bit2bin import bit2bin
1211

@@ -18,13 +17,13 @@ def get_argparser():
1817
epilog="""\
1918
Valid actions:
2019
21-
* proxy: load the flash proxy bitstream
22-
* bitstream: write bitstream to flash
20+
* proxy: load the flash proxy gateware bitstream
21+
* gateware: write gateware bitstream to flash
2322
* bios: write bios to flash
2423
* runtime: write runtime to flash
2524
* storage: write storage image to flash
26-
* load: load bitstream into device (volatile but fast)
27-
* start: trigger the target to (re)load its bitstream from flash
25+
* load: load gateware bitstream into device (volatile but fast)
26+
* start: trigger the target to (re)load its gateware bitstream from flash
2827
2928
Prerequisites:
3029
@@ -37,12 +36,12 @@ def get_argparser():
3736
""")
3837
parser.add_argument("-t", "--target", default="kc705",
3938
help="target board, default: %(default)s")
40-
parser.add_argument("-m", "--adapter", default="qc2",
39+
parser.add_argument("-m", "--adapter", default="clock",
4140
help="target adapter, default: %(default)s")
4241
parser.add_argument("-f", "--storage", help="write file to storage area")
4342
parser.add_argument("-d", "--dir", help="look for files in this directory")
4443
parser.add_argument("ACTION", nargs="*",
45-
default="proxy bitstream bios runtime start".split(),
44+
default="proxy gateware bios runtime start".split(),
4645
help="actions to perform, default: %(default)s")
4746
return parser
4847

@@ -55,15 +54,15 @@ def main():
5554
"kc705": {
5655
"chip": "xc7k325t",
5756
"start": "xc7_program xc7.tap",
58-
"bitstream": 0x000000,
57+
"gateware": 0x000000,
5958
"bios": 0xaf0000,
6059
"runtime": 0xb00000,
6160
"storage": 0xb80000,
6261
},
6362
"pipistrello": {
6463
"chip": "xc6slx45",
6564
"start": "xc6s_program xc6s.tap",
66-
"bitstream": 0x000000,
65+
"gateware": 0x000000,
6766
"bios": 0x170000,
6867
"runtime": 0x180000,
6968
"storage": 0x200000,
@@ -83,23 +82,23 @@ def main():
8382
proxy_base = "bscan_spi_{}.bit".format(config["chip"])
8483
proxy = None
8584
for p in [opts.dir, os.path.expanduser("~/.migen"),
86-
"/usr/local/share/migen", "/usr/share/migen"]:
85+
"/usr/local/share/migen", "/usr/share/migen"]:
8786
proxy_ = os.path.join(p, proxy_base)
8887
if os.access(proxy_, os.R_OK):
8988
proxy = "jtagspi_init 0 {}".format(proxy_)
9089
break
9190
if not proxy:
9291
raise SystemExit(
93-
"proxy bitstream {} not found".format(proxy_base))
92+
"proxy gateware bitstream {} not found".format(proxy_base))
9493
prog.append(proxy)
95-
elif action == "bitstream":
94+
elif action == "gateware":
9695
bin = os.path.join(opts.dir, "top.bin")
9796
if not os.access(bin, os.R_OK):
9897
bin = tempfile.mkstemp()[1]
9998
bit = os.path.join(opts.dir, "top.bit")
10099
conv = True
101100
prog.append("jtagspi_program {} 0x{:x}".format(
102-
bin, config["bitstream"]))
101+
bin, config["gateware"]))
103102
elif action == "bios":
104103
prog.append("jtagspi_program {} 0x{:x}".format(
105104
os.path.join(opts.dir, "bios.bin"), config["bios"]))

‎artiq/gateware/nist_clock.py

+2-4
Original file line numberDiff line numberDiff line change
@@ -48,10 +48,8 @@
4848
Subsignal("n", Pins("LPC:CLK1_M2C_N")),
4949
IOStandard("LVDS")),
5050

51-
("la32", 0,
52-
Subsignal("p", Pins("LPC:LA32_P")),
53-
Subsignal("n", Pins("LPC:LA32_N")),
54-
IOStandard("LVDS")),
51+
("la32_p", 0, Pins("LPC:LA32_P"), IOStandard("LVTTL")),
52+
("la32_n", 0, Pins("LPC:LA32_N"), IOStandard("LVTTL")),
5553

5654
("spi", 0,
5755
Subsignal("clk", Pins("LPC:LA13_N")),

‎artiq/gateware/targets/kc705.py

+6-3
Original file line numberDiff line numberDiff line change
@@ -249,20 +249,23 @@ def __init__(self, cpu_type="or1k", **kwargs):
249249
phy = ttl_simple.Output(platform.request("user_led", 2))
250250
self.submodules += phy
251251
rtio_channels.append(rtio.Channel.from_phy(phy))
252-
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
253252

254253
spi_pins = self.platform.request("ams101_dac", 0)
255254
phy = ttl_simple.Output(spi_pins.ldac)
256255
self.submodules += phy
257-
self.config["RTIO_SPI_LDAC_CHANNEL"] = len(rtio_channels)
258256
rtio_channels.append(rtio.Channel.from_phy(phy))
257+
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
259258

260259
phy = spi.SPIMaster(spi_pins)
261260
self.submodules += phy
262261
self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
263262
rtio_channels.append(rtio.Channel.from_phy(
264263
phy, ofifo_depth=4, ififo_depth=4))
265264

265+
phy = ttl_simple.ClockGen(platform.request("la32_p"))
266+
self.submodules += phy
267+
rtio_channels.append(rtio.Channel.from_phy(phy))
268+
266269
self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
267270
self.config["DDS_CHANNEL_COUNT"] = 11
268271
self.config["DDS_AD9914"] = True
@@ -341,7 +344,7 @@ def main():
341344
"+ NIST Ions QC1/CLOCK/QC2 hardware adapters")
342345
builder_args(parser)
343346
soc_kc705_args(parser)
344-
parser.add_argument("-H", "--hw-adapter", default="qc1",
347+
parser.add_argument("-H", "--hw-adapter", default="clock",
345348
help="hardware adapter type: qc1/clock/qc2 "
346349
"(default: %(default)s)")
347350
args = parser.parse_args()

‎artiq/master/scheduler.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ async def _do(self):
198198
await self.pool.state_changed.wait()
199199
elif isinstance(run, float):
200200
await asyncio_wait_or_cancel([self.pool.state_changed.wait()],
201-
timeout=run)
201+
timeout=run)
202202
else:
203203
if run.flush:
204204
run.status = RunStatus.flushing

‎artiq/runtime/main.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -137,9 +137,9 @@ static void network_init(void)
137137
struct ip4_addr gateway_ip;
138138

139139
init_macadr();
140-
fsip_or_default(&local_ip, "ip", 192, 168, 0, 42);
140+
fsip_or_default(&local_ip, "ip", 192, 168, 1, 50);
141141
fsip_or_default(&netmask, "netmask", 255, 255, 255, 0);
142-
fsip_or_default(&gateway_ip, "gateway", 192, 168, 0, 1);
142+
fsip_or_default(&gateway_ip, "gateway", 192, 168, 1, 1);
143143

144144
lwip_init();
145145

‎doc/manual/core_device.rst

+2
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,8 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
6464
+--------------------+-----------------------+--------------+
6565
| 19 | LED | Output |
6666
+--------------------+-----------------------+--------------+
67+
| 20 | LA32_P | Clock |
68+
+--------------------+-----------------------+--------------+
6769

6870

6971
Pipistrello

‎doc/manual/getting_started_core.rst

+4
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,10 @@ Create a new file ``rtio.py`` containing the following: ::
108108
delay(2*us)
109109

110110

111+
.. note::
112+
If ``ttl0`` is a bidirectional channel (``TTLInOut``), it is in input (non-driving) mode by default. You need to call ``self.ttl0.output()`` as explained above for the LED.
113+
114+
111115
Connect an oscilloscope or logic analyzer to TTL0 and run ``artiq_run.py led.py``. Notice that the generated signal's period is precisely 4 microseconds, and that it has a duty cycle of precisely 50%. This is not what you would expect if the delay and the pulse were implemented with CPU-controlled GPIO: overhead from the loop management, function calls, etc. would increase the signal's period, and asymmetry in the overhead would cause duty cycle distortion.
112116

113117
Instead, inside the core device, output timing is generated by the gateware and the CPU only programs switching commands with certain timestamps that the CPU computes. This guarantees precise timing as long as the CPU can keep generating timestamps that are increasing fast enough. In case it fails to do that (and attempts to program an event with a timestamp in the past), the :class:`artiq.coredevice.exceptions.RTIOUnderflow` exception is raised. The kernel causing it may catch it (using a regular ``try... except...`` construct), or it will be propagated to the host.

‎doc/manual/installing.rst

+17-9
Original file line numberDiff line numberDiff line change
@@ -40,13 +40,16 @@ If your ``$PATH`` misses reference the ``miniconda3/bin`` or ``anaconda3/bin`` y
4040

4141
$ export PATH=$HOME/miniconda3/bin:$PATH
4242

43-
Installing the host side software
44-
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
43+
Installing the ARTIQ packages
44+
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
4545

4646
For this, you need to add our Anaconda repository to your conda configuration::
4747

4848
$ conda config --add channels http://conda.anaconda.org/m-labs/channel/main
49-
$ conda config --add channels http://conda.anaconda.org/m-labs/channel/dev
49+
50+
.. note::
51+
To use the development versions of ARTIQ, also add the ``dev`` channel (http://conda.anaconda.org/m-labs/channel/dev).
52+
Development versions contain more features, but are not as well-tested and are more likely to contain bugs or inconsistencies.
5053

5154
Then you can install the ARTIQ package, it will pull all the necessary dependencies.
5255

@@ -60,7 +63,12 @@ Then you can install the ARTIQ package, it will pull all the necessary dependenc
6063
$ ENV=$(date +artiq-%Y-%m-%d); conda create -n $ENV artiq-kc705-nist_qc1; \
6164
echo "Created environment $ENV for ARTIQ"
6265

63-
* For the KC705 board with the FMC backplane and AD9914 DDS chips::
66+
* For the KC705 board with the "clock" FMC backplane and AD9914 DDS chips::
67+
68+
$ ENV=$(date +artiq-%Y-%m-%d); conda create -n $ENV artiq-kc705-nist_clock; \
69+
echo "Created environment $ENV for ARTIQ"
70+
71+
* For the KC705 board with the QC2 FMC backplane and AD9914 DDS chips::
6472

6573
$ ENV=$(date +artiq-%Y-%m-%d); conda create -n $ENV artiq-kc705-nist_qc2; \
6674
echo "Created environment $ENV for ARTIQ"
@@ -89,19 +97,19 @@ You now need to flash 3 things on the FPGA board:
8997
2. The BIOS
9098
3. The ARTIQ runtime
9199

92-
First you need to :ref:`install openocd <install-openocd>`. Then, you can flash the board:
100+
They are all shipped in our Conda packages, along with the required flash proxy bitstreams.
101+
102+
First you need to install OpenOCD. Then, you can flash the board:
93103

94104
* For the Pipistrello board::
95105

96106
$ artiq_flash -t pipistrello
97107

98108
* For the KC705 board::
99109

100-
$ artiq_flash
101-
102-
Next step (for KC705) is to flash MAC and IP addresses to the board:
110+
$ artiq_flash -m [qc1/clock/qc2]
103111

104-
* See :ref:`those instructions <flash-mac-ip-addr>` to flash MAC and IP addresses.
112+
For the KC705, the next step is to flash the MAC and IP addresses to the board. See :ref:`those instructions <flash-mac-ip-addr>`.
105113

106114
.. _install-from-sources:
107115

‎examples/master/device_db.pyon

+43-34
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
11
# This is an example device database that needs to be adapted to your setup.
2-
# The RTIO channel numbers here are for NIST QC1 on KC705.
2+
# The RTIO channel numbers here are for NIST CLOCK on KC705.
33

44
{
55
"comm": {
66
"type": "local",
77
"module": "artiq.coredevice.comm_tcp",
88
"class": "Comm",
9-
"arguments": {"host": "192.168.0.42"}
9+
"arguments": {"host": "kc705.lab.m-labs.hk"}
1010
},
1111
"core": {
1212
"type": "local",
@@ -15,73 +15,77 @@
1515
"arguments": {"ref_period": 1e-9}
1616
},
1717

18-
"pmt0": {
19-
"type": "local",
20-
"module": "artiq.coredevice.ttl",
21-
"class": "TTLInOut",
22-
"arguments": {"channel": 0}
23-
},
24-
"pmt1": {
25-
"type": "local",
26-
"module": "artiq.coredevice.ttl",
27-
"class": "TTLInOut",
28-
"arguments": {"channel": 1}
29-
},
30-
3118
"ttl0": {
3219
"type": "local",
3320
"module": "artiq.coredevice.ttl",
3421
"class": "TTLOut",
35-
"arguments": {"channel": 2},
22+
"arguments": {"channel": 0},
3623
"comment": "This is a fairly long comment to test word wrapping in GUI."
3724
},
3825
"ttl1": {
3926
"type": "local",
4027
"module": "artiq.coredevice.ttl",
4128
"class": "TTLOut",
42-
"arguments": {"channel": 3},
29+
"arguments": {"channel": 1},
4330
"comment": "Hello World"
4431
},
4532
"ttl2": {
4633
"type": "local",
4734
"module": "artiq.coredevice.ttl",
4835
"class": "TTLOut",
49-
"arguments": {"channel": 4}
36+
"arguments": {"channel": 2}
5037
},
5138
"ttl3": {
5239
"type": "local",
5340
"module": "artiq.coredevice.ttl",
54-
"class": "TTLOut",
55-
"arguments": {"channel": 5}
41+
"class": "TTLInOut",
42+
"arguments": {"channel": 3}
5643
},
44+
5745
"ttl4": {
5846
"type": "local",
5947
"module": "artiq.coredevice.ttl",
6048
"class": "TTLOut",
61-
"arguments": {"channel": 6}
49+
"arguments": {"channel": 4}
6250
},
6351
"ttl5": {
6452
"type": "local",
6553
"module": "artiq.coredevice.ttl",
6654
"class": "TTLOut",
67-
"arguments": {"channel": 7}
55+
"arguments": {"channel": 5}
6856
},
69-
"ttl_sma": {
57+
"ttl6": {
58+
"type": "local",
59+
"module": "artiq.coredevice.ttl",
60+
"class": "TTLOut",
61+
"arguments": {"channel": 6}
62+
},
63+
"ttl7": {
7064
"type": "local",
7165
"module": "artiq.coredevice.ttl",
7266
"class": "TTLInOut",
73-
"arguments": {"channel": 17}
67+
"arguments": {"channel": 7}
7468
},
75-
"led": {
69+
70+
71+
"ttl_sma": {
7672
"type": "local",
7773
"module": "artiq.coredevice.ttl",
78-
"class": "TTLOut",
74+
"class": "TTLInOut",
7975
"arguments": {"channel": 18}
8076
},
81-
"ttl15": {
77+
"ttl_clock_la32_p": {
8278
"type": "local",
8379
"module": "artiq.coredevice.ttl",
8480
"class": "TTLClockGen",
81+
"arguments": {"channel": 20}
82+
},
83+
84+
85+
"led": {
86+
"type": "local",
87+
"module": "artiq.coredevice.ttl",
88+
"class": "TTLOut",
8589
"arguments": {"channel": 19}
8690
},
8791

@@ -94,21 +98,21 @@
9498
"dds0": {
9599
"type": "local",
96100
"module": "artiq.coredevice.dds",
97-
"class": "AD9858",
98-
"arguments": {"sysclk": 1e9, "channel": 0},
101+
"class": "AD9914",
102+
"arguments": {"sysclk": 3e9, "channel": 0},
99103
"comment": "Comments work in DDS panel as well"
100104
},
101105
"dds1": {
102106
"type": "local",
103107
"module": "artiq.coredevice.dds",
104-
"class": "AD9858",
105-
"arguments": {"sysclk": 1e9, "channel": 1}
108+
"class": "AD9914",
109+
"arguments": {"sysclk": 3e9, "channel": 1}
106110
},
107111
"dds2": {
108112
"type": "local",
109113
"module": "artiq.coredevice.dds",
110-
"class": "AD9858",
111-
"arguments": {"sysclk": 1e9, "channel": 2}
114+
"class": "AD9914",
115+
"arguments": {"sysclk": 3e9, "channel": 2}
112116
},
113117

114118
"qc_q1_0": {
@@ -160,7 +164,12 @@
160164
"ttl_out": "ttl0",
161165
"ttl_out_serdes": "ttl0",
162166

163-
"pmt": "pmt0",
167+
"loop_out": "ttl0",
168+
"loop_in": "ttl3",
169+
"loop_clock_out": "ttl_clock_la32_p",
170+
"loop_clock_in": "ttl7",
171+
172+
"pmt": "ttl3",
164173
"bd_dds": "dds0",
165174
"bd_sw": "ttl0",
166175
"bdd_dds": "dds1",

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