m-labs · Mar 4, 2016 · Mar 4, 2016 · Mar 4, 2016 · Mar 4, 2016 · Mar 4, 2016
Showing with 100 additions and 27 deletions.

+4 −0 artiq/coredevice/exceptions.py

+75 −0 artiq/coredevice/i2c.py

+11 −16 artiq/gateware/targets/kc705.py

+1 −1 artiq/master/worker_db.py

+6 −7 artiq/runtime/i2c.c

+3 −3 artiq/runtime/i2c.h
diff --git a/artiq/coredevice/exceptions.py b/artiq/coredevice/exceptions.py
@@ -113,3 +113,7 @@ class DDSBatchError(Exception):
     or when too many commands are batched.
     """
     artiq_builtin = True
+
+class I2CError(Exception):
+    """Raised with a I2C transaction fails."""
+    artiq_builtin = True
diff --git a/artiq/coredevice/i2c.py b/artiq/coredevice/i2c.py
@@ -0,0 +1,75 @@
+from artiq.language.core import syscall, kernel
+from artiq.language.types import TBool, TInt8, TInt32, TNone
+from artiq.coredevice.exceptions import I2CError
+
+
+@syscall
+def i2c_init(busno: TInt32) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall
+def i2c_start(busno: TInt32) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall
+def i2c_stop(busno: TInt32) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall
+def i2c_write(busno: TInt32, b: TInt32) -> TBool:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall
+def i2c_read(busno: TInt32, ack: TBool) -> TInt32:
+    raise NotImplementedError("syscall not simulated")
+
+
+class PCA9548:
+    def __init__(self, dmgr, busno=0, address=0x74):
+        self.core = dmgr.get("core")
+        self.busno = busno
+        self.address = address
+
+    @kernel
+    def set(self, channel):
+        i2c_init(self.busno)
+        i2c_start(self.busno)
+        try:
+            if not i2c_write(self.busno, self.address):
+                raise I2CError("PCA9548 failed to ack address")
+            if not i2c_write(self.busno, 1 << channel):
+                raise I2CError("PCA9548 failed to ack control word")
+        finally:
+            i2c_stop(self.busno)
+
+
+class TCA6424A:
+    def __init__(self, dmgr, busno=0, address=0x44):
+        self.core = dmgr.get("core")
+        self.busno = busno
+        self.address = address
+
+    @kernel
+    def _write24(self, command, value):
+        i2c_init(self.busno)
+        i2c_start(self.busno)
+        try:
+            if not i2c_write(self.busno, self.address):
+                raise I2CError("TCA6424A failed to ack address")
+            if not i2c_write(self.busno, command):
+                raise I2CError("TCA6424A failed to ack command")
+            for i in range(3):
+                if not i2c_write(self.busno, value >> 16):
+                    raise I2CError("TCA6424A failed to ack command")
+                value <<= 8
+        finally:
+            i2c_stop(self.busno)
+
+    @kernel
+    def set(self, outputs):
+        self._write24(0x8c, 0)  # set all directions to output
+        self._write24(0x84, output)  # set levels
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -94,8 +94,11 @@ def __init__(self, platform, rtio_internal_clk):
 
 class _NIST_Ions(MiniSoC, AMPSoC):
     csr_map = {
-        "timer_kernel": None,  # mapped on Wishbone instead
-        "rtio": None,  # mapped on Wishbone instead
+        # mapped on Wishbone instead
+        "timer_kernel": None,
+        "rtio": None,
+        "i2c": None,
+
         "rtio_crg": 13,
         "kernel_cpu": 14,
         "rtio_moninj": 15,
@@ -105,6 +108,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
     mem_map = {
         "timer_kernel":  0x10000000, # (shadow @0x90000000)
         "rtio":          0x20000000, # (shadow @0xa0000000)
+        "i2c":           0x30000000, # (shadow @0xb0000000)
         "mailbox":       0x70000000  # (shadow @0xf0000000)
     }
     mem_map.update(MiniSoC.mem_map)
@@ -131,6 +135,11 @@ def __init__(self, cpu_type="or1k", **kwargs):
 
         self.platform.add_extension(_ams101_dac)
 
+        i2c = self.platform.request("i2c")
+        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
+        self.register_kernel_cpu_csrdevice("i2c")
+        self.config["I2C_BUS_COUNT"] = 1
+
     def add_rtio(self, rtio_channels):
         self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
         self.submodules.rtio = rtio.RTIO(rtio_channels)
@@ -293,15 +302,6 @@ class NIST_QC2(_NIST_Ions):
     NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
     and 12 DDS channels. Current implementation for single backplane.
     """
-    csr_map = {
-        "i2c": None
-    }
-    csr_map.update(_NIST_Ions.csr_map)
-    mem_map = {
-        "i2c":  0x30000000 # (shadow @0xb0000000)
-    }
-    mem_map.update(_NIST_Ions.mem_map)
-
     def __init__(self, cpu_type="or1k", **kwargs):
         _NIST_Ions.__init__(self, cpu_type, **kwargs)
 
@@ -350,11 +350,6 @@ def __init__(self, cpu_type="or1k", **kwargs):
         assert self.rtio.fine_ts_width <= 3
         self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width
 
-        i2c = platform.request("i2c")
-        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
-        self.register_kernel_cpu_csrdevice("i2c")
-        self.config["I2C_BUS_COUNT"] = 1
-
 
 def main():
     parser = argparse.ArgumentParser(

diff --git a/artiq/master/worker_db.py b/artiq/master/worker_db.py
@@ -90,7 +90,7 @@ def _create_device(desc, device_mgr):
     if ty == "local":
         module = importlib.import_module(desc["module"])
         device_class = getattr(module, desc["class"])
-        return device_class(device_mgr, **desc["arguments"])
+        return device_class(device_mgr, **desc.get("arguments", {}))
     elif ty == "controller":
         if desc.get("best_effort", False):
             cls = BestEffortClient

diff --git a/artiq/runtime/i2c.c b/artiq/runtime/i2c.c
@@ -1,5 +1,6 @@
 #include <generated/csr.h>
 
+#include "artiq_personality.h"
 #include "rtio.h"
 #include "i2c.h"
 
@@ -91,7 +92,7 @@ static void i2c_scl_o(int busno, int o) {}
 #endif
 
 
-int i2c_init(int busno)
+void i2c_init(int busno)
 {
     /* Set SCL as output, and high level */
     i2c_scl_o(busno, 1);
@@ -104,10 +105,8 @@ int i2c_init(int busno)
     /* Check the I2C bus is ready */
     i2c_halfperiod();
     i2c_halfperiod();
-    if(i2c_sda_i(busno))
-        return 1; /* success */
-    else
-        return 0;
+    if(!i2c_sda_i(busno))
+        artiq_raise_from_c("I2CError", "SDA is stuck low", 0, 0, 0);
 }
 
 void i2c_start(int busno)
@@ -132,7 +131,7 @@ void i2c_stop(int busno)
     i2c_halfperiod();
 }
 
-int i2c_write(int busno, char b)
+int i2c_write(int busno, int b)
 {
     int i;
 
@@ -158,7 +157,7 @@ int i2c_write(int busno, char b)
     return !i2c_sda_i(busno);
 }
 
-char i2c_read(int busno, int ack)
+int i2c_read(int busno, int ack)
 {
     int i;
     char b;

diff --git a/artiq/runtime/i2c.h b/artiq/runtime/i2c.h
@@ -1,10 +1,10 @@
 #ifndef __I2C_H
 #define __I2C_H
 
-int i2c_init(int busno);
+void i2c_init(int busno);
 void i2c_start(int busno);
 void i2c_stop(int busno);
-int i2c_write(int busno, char b);
-char i2c_read(int busno, int ack);
+int i2c_write(int busno, int b);
+int i2c_read(int busno, int ack);
 
 #endif