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  • 2 commits
  • 13 files changed
  • 1 contributor

Commits on Mar 4, 2016

  1. interconnect/cores: Remove use of Record.connect() 

    Keep Sink/Source classes for now since it is still necessary to do the distinction
we'll try to only use Endpoint later.
    @enjoy-digital
    enjoy-digital committed Mar 4, 2016
    1
    Copy the full SHA
    29f6d2d View commit details

  2. cores/liteeth_mini: fix mii phy (broken since misoc refactoring)

    @enjoy-digital
    enjoy-digital committed Mar 4, 2016
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    0f14dbe View commit details
4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/common.py
View file
Original file line number Diff line number Diff line change
@@ -8,8 +8,8 @@
class Port:
def connect(self, port):
r = [
Record.connect(self.source, port.sink),
Record.connect(port.source, self.sink)
self.source.connect(port.sink),
port.source.connect(self.sink)
]
return r

4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/mac/core/crc.py
View file
Original file line number Diff line number Diff line change
@@ -161,7 +161,7 @@ def __init__(self, crc_class, description):
fsm.act("COPY",
crc.ce.eq(sink.stb & source.ack),
crc.data.eq(sink.data),
Record.connect(sink, source),
sink.connect(source),
source.eop.eq(0),
If(sink.stb & sink.eop & source.ack,
NextState("INSERT"),
@@ -246,7 +246,7 @@ def __init__(self, crc_class, description):
fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
fifo_out.eq(source.stb & source.ack),

Record.connect(sink, fifo.sink),
sink.connect(fifo.sink),
fifo.sink.stb.eq(fifo_in),
self.sink.ack.eq(fifo_in),

2 changes: 1 addition & 1 deletion misoc/cores/liteeth_mini/mac/core/gap.py
View file
Original file line number Diff line number Diff line change
@@ -28,7 +28,7 @@ def __init__(self, dw, ack_on_gap=False):
self.submodules.fsm = fsm = FSM(reset_state="COPY")
fsm.act("COPY",
counter_reset.eq(1),
Record.connect(sink, source),
sink.connect(source),
If(sink.stb & sink.eop & sink.ack,
NextState("GAP")
)
4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/mac/core/padding.py
View file
Original file line number Diff line number Diff line change
@@ -32,7 +32,7 @@ def __init__(self, dw, padding):

self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
Record.connect(sink, source),
sink.connect(source),
If(source.stb & source.ack,
counter_ce.eq(1),
If(sink.eop,
@@ -64,5 +64,5 @@ def __init__(self, dw, packet_min_length):

# TODO: see if we should drop the packet when
# payload size < minimum ethernet payload size
self.comb += Record.connect(sink, source)
self.comb += sink.connect(source)

4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/mac/core/preamble.py
View file
Original file line number Diff line number Diff line change
@@ -53,7 +53,7 @@ def __init__(self, dw):
self.source.last_be.eq(self.sink.last_be)
]
fsm.act("COPY",
Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
self.sink.connect(self.source, leave_out=set(["data", "last_be"])),
self.source.sop.eq(0),

If(self.sink.stb & self.sink.eop & self.source.ack,
@@ -146,7 +146,7 @@ def __init__(self, dw):
self.source.last_be.eq(self.sink.last_be)
]
fsm.act("COPY",
Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
self.sink.connect(self.source, leave_out=set(["data", "last_be"])),
self.source.sop.eq(sop),
clr_sop.eq(self.source.stb & self.source.ack),

4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/mac/frontend/wishbone.py
View file
Original file line number Diff line number Diff line change
@@ -20,8 +20,8 @@ def __init__(self, dw, nrxslots=2, ntxslots=2):
sram_depth = buffer_depth//(dw//8)
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
self.comb += [
Record.connect(self.sink, self.sram.sink),
Record.connect(self.sram.source, self.source)
self.sink.connect(self.sram.sink),
self.sram.source.connect(self.source)
]

# Wishbone interface
12 changes: 6 additions & 6 deletions misoc/cores/liteeth_mini/phy/gmii_mii.py
View file
Original file line number Diff line number Diff line change
@@ -36,9 +36,9 @@ def __init__(self, pads, mode):
self.submodules += demux
self.comb += [
demux.sel.eq(mode == modes["MII"]),
Record.connect(sink, demux.sink),
Record.connect(demux.source0, gmii_tx.sink),
Record.connect(demux.source1, mii_tx.sink),
sink.connect(demux.sink),
demux.source0.connect(gmii_tx.sink),
demux.source1.connect(mii_tx.sink),
]

if hasattr(pads, "tx_er"):
@@ -76,9 +76,9 @@ def __init__(self, pads, mode):
self.submodules += mux
self.comb += [
mux.sel.eq(mode == modes["MII"]),
Record.connect(gmii_rx.source, mux.sink0),
Record.connect(mii_rx.source, mux.sink1),
Record.connect(mux.source, source)
gmii_rx.source.connect(mux.sink0),
mii_rx.source.connect(mux.sink1),
mux.source.connect(source)
]


2 changes: 1 addition & 1 deletion misoc/cores/liteeth_mini/phy/loopback.py
View file
Original file line number Diff line number Diff line change
@@ -32,4 +32,4 @@ def __init__(self):
self.submodules.crg = LiteEthLoopbackPHYCRG()
self.sink = Sink(eth_phy_description(8))
self.source = Source(eth_phy_description(8))
self.comb += Record.connect(self.sink, self.source)
self.comb += self.sink.connect(self.source)
11 changes: 7 additions & 4 deletions misoc/cores/liteeth_mini/phy/mii.py
View file
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer

from misoc.interconnect.csr import *
from misoc.interconnect.stream import *
@@ -66,7 +67,7 @@ def __init__(self, pads):
converter.sink.sop.eq(sop),
converter.sink.eop.eq(~pads.dv)
]
self.comb += Record.connect(converter.source, source)
self.comb += converter.source.connect(source)


class LiteEthPHYMIICRG(Module, AutoCSR):
@@ -85,11 +86,13 @@ def __init__(self, clock_pads, pads, with_hw_init_reset):

if with_hw_init_reset:
reset = Signal()
counter = Signal(max=512)
counter_done = Signal()
self.submodules.counter = counter = Counter(max=512)
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter.value == 256),
counter.ce.eq(~counter_done),
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
else:
8 changes: 4 additions & 4 deletions misoc/cores/sdram_phy/s6ddrphy.py
View file
Original file line number Diff line number Diff line change
@@ -453,11 +453,11 @@ def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"])
self.comb += [
If(~phase_sel,
Record.connect(self.dfi.phases[0], half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
Record.connect(self.dfi.phases[1], half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
self.dfi.phases[0].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
self.dfi.phases[1].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
).Else(
Record.connect(self.dfi.phases[2], half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
Record.connect(self.dfi.phases[3], half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
self.dfi.phases[2].connect(half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
self.dfi.phases[3].connect(half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
),
]
wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel
4 changes: 2 additions & 2 deletions misoc/cores/uart/core.py
View file
Original file line number Diff line number Diff line change
@@ -143,7 +143,7 @@ def __init__(self, phy,
tx_fifo.sink.stb.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ack),
Record.connect(tx_fifo.source, phy.sink),
tx_fifo.source.connect(phy.sink),
# Generate TX IRQ when tx_fifo becomes non-full
self.ev.tx.trigger.eq(~tx_fifo.sink.ack)
]
@@ -153,7 +153,7 @@ def __init__(self, phy,
self.submodules += rx_fifo

self.comb += [
Record.connect(phy.source, rx_fifo.sink),
phy.source.connect(rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.stb),
self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ack.eq(self.ev.rx.clear),
28 changes: 13 additions & 15 deletions misoc/interconnect/stream.py
View file
Original file line number Diff line number Diff line change
@@ -53,14 +53,12 @@ def __getattr__(self, name):
return getattr(object.__getattribute__(self, "payload"), name)


class Source(Endpoint): # deprecated
def connect(self, sink):
return Record.connect(self, sink)
class Source(Endpoint):
pass


class Sink(Endpoint): # deprecated
def connect(self, source):
return source.connect(self)
class Sink(Endpoint):
pass


class _FIFOWrapper(Module):
@@ -129,7 +127,7 @@ def __init__(self, layout, n):

cases = {}
for i, sink in enumerate(sinks):
cases[i] = Record.connect(sink, self.source)
cases[i] = sink.connect(self.source)
self.comb += Case(self.sel, cases)


@@ -147,7 +145,7 @@ def __init__(self, layout, n):

cases = {}
for i, source in enumerate(sources):
cases[i] = Record.connect(self.sink, source)
cases[i] = self.sink.connect(source)
self.comb += Case(self.sel, cases)

# TODO: clean up code below
@@ -361,9 +359,9 @@ def __init__(self, layout_from, layout_to, reverse=False):
self.submodules.unpack = Unpack(ratio, layout_to)

self.comb += [
Record.connect(self.sink, self.chunkerize.sink),
Record.connect(self.chunkerize.source, self.unpack.sink),
Record.connect(self.unpack.source, self.source),
self.sink.connect(self.chunkerize.sink),
self.chunkerize.source.connect(self.unpack.sink),
self.unpack.source.connect(self.source),
self.busy.eq(self.unpack.busy)
]
# upconverter
@@ -375,13 +373,13 @@ def __init__(self, layout_from, layout_to, reverse=False):
self.submodules.unchunkerize = Unchunkerize(layout_from, ratio, layout_to, reverse)

self.comb += [
Record.connect(self.sink, self.pack.sink),
Record.connect(self.pack.source, self.unchunkerize.sink),
Record.connect(self.unchunkerize.source, self.source),
self.sink.connect(self.pack.sink),
self.pack.source.connect(self.unchunkerize.sink),
self.unchunkerize.source.connect(self.source),
self.busy.eq(self.pack.busy)
]
# direct connection
else:
self.comb += Record.connect(self.sink, self.source)
self.comb += self.sink.connect(self.source)

# XXX
2 changes: 1 addition & 1 deletion misoc/interconnect/wishbone.py
View file
Original file line number Diff line number Diff line change
@@ -449,7 +449,7 @@ def __init__(self, master, slave):
upconverter = UpConverter(master, slave)
self.submodules += upconverter
else:
Record.connect(master, slave)
master.connect(slave)


class Cache(Module):