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test: rewrite tests using ttl_inout to use loop_{in,out} (#265).
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whitequark committed Feb 24, 2016
1 parent a829b8a commit 652c2a1
Showing 3 changed files with 6 additions and 49 deletions.
11 changes: 5 additions & 6 deletions artiq/test/coredevice/test_analyzer.py
Original file line number Diff line number Diff line change
@@ -6,18 +6,17 @@
class CreateTTLPulse(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("ttl_inout")
self.setattr_device("loop_in")
self.setattr_device("loop_out")

@kernel
def run(self):
self.ttl_inout.output()
delay_mu(100)
with parallel:
self.ttl_inout.gate_both_mu(1200)
self.loop_in.gate_both_mu(1200)
with sequential:
delay_mu(100)
self.ttl_inout.pulse_mu(1000)
self.ttl_inout.count()
self.loop_out.pulse_mu(1000)
self.loop_in.count()


class AnalyzerTest(ExperimentCase):
43 changes: 1 addition & 42 deletions artiq/test/coredevice/test_rtio.py
Original file line number Diff line number Diff line change
@@ -20,7 +20,7 @@ def build(self):
def run(self):
self.ttl_inout.output()
delay(1*us)
with parallel:
with interleave:
# make sure not to send two commands into the same RTIO
# channel with the same timestamp
self.ttl_inout.gate_rising(5*us)
@@ -101,28 +101,6 @@ def run(self):
pass


class LoopbackCount(EnvExperiment):

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@sbourdeauducq

sbourdeauducq Feb 25, 2016

Member

Please keep this test.

def build(self):
self.setattr_device("core")
self.setattr_device("ttl_inout")
self.setattr_argument("npulses")

def set_count(self, count):
self.set_dataset("count", count)

@kernel
def run(self):
self.ttl_inout.output()
delay(5*us)
with parallel:
self.ttl_inout.gate_rising(10*us)
with sequential:
for i in range(self.npulses):
delay(25*ns)
self.ttl_inout.pulse(25*ns)
self.set_dataset("count", self.ttl_inout.count())


class Underflow(EnvExperiment):
def build(self):
self.setattr_device("core")
@@ -185,17 +163,6 @@ def run(self):


class CoredeviceTest(ExperimentCase):
@unittest.skipUnless(artiq_low_latency,
"timings are dependent on CPU load and network conditions")
def test_rtt(self):
self.execute(RTT)
rtt = self.dataset_mgr.get("rtt")
print(rtt)
self.assertGreater(rtt, 0*ns)
self.assertLess(rtt, 100*ns)

@unittest.skipUnless(artiq_low_latency,
"timings are dependent on CPU load and network conditions")
def test_loopback(self):
self.execute(Loopback)
rtt = self.dataset_mgr.get("rtt")
@@ -208,21 +175,13 @@ def test_clock_generator_loopback(self):
count = self.dataset_mgr.get("count")
self.assertEqual(count, 10)

@unittest.skipUnless(artiq_low_latency,
"timings are dependent on CPU load and network conditions")
def test_pulse_rate(self):
self.execute(PulseRate)
rate = self.dataset_mgr.get("pulse_rate")
print(rate)
self.assertGreater(rate, 100*ns)
self.assertLess(rate, 2500*ns)

def test_loopback_count(self):
npulses = 2
self.execute(LoopbackCount, npulses=npulses)
count = self.dataset_mgr.get("count")
self.assertEqual(count, npulses)

def test_underflow(self):
with self.assertRaises(RTIOUnderflow):
self.execute(Underflow)
1 change: 0 additions & 1 deletion examples/master/device_db.pyon
Original file line number Diff line number Diff line change
@@ -157,7 +157,6 @@
"command": "lda_controller -p {port} --bind {bind} --simulation"
},

"ttl_inout": "pmt0",
"ttl_out": "ttl0",
"ttl_out_serdes": "ttl0",

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