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author
whitequark
committedFeb 24, 2016
test: rewrite tests using ttl_inout to use loop_{in,out} (#265).
1 parent a829b8a commit 652c2a1

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3 files changed

+6
-49
lines changed

3 files changed

+6
-49
lines changed
 

‎artiq/test/coredevice/test_analyzer.py

+5-6
Original file line numberDiff line numberDiff line change
@@ -6,18 +6,17 @@
66
class CreateTTLPulse(EnvExperiment):
77
def build(self):
88
self.setattr_device("core")
9-
self.setattr_device("ttl_inout")
9+
self.setattr_device("loop_in")
10+
self.setattr_device("loop_out")
1011

1112
@kernel
1213
def run(self):
13-
self.ttl_inout.output()
14-
delay_mu(100)
1514
with parallel:
16-
self.ttl_inout.gate_both_mu(1200)
15+
self.loop_in.gate_both_mu(1200)
1716
with sequential:
1817
delay_mu(100)
19-
self.ttl_inout.pulse_mu(1000)
20-
self.ttl_inout.count()
18+
self.loop_out.pulse_mu(1000)
19+
self.loop_in.count()
2120

2221

2322
class AnalyzerTest(ExperimentCase):

‎artiq/test/coredevice/test_rtio.py

+1-42
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ def build(self):
2020
def run(self):
2121
self.ttl_inout.output()
2222
delay(1*us)
23-
with parallel:
23+
with interleave:
2424
# make sure not to send two commands into the same RTIO
2525
# channel with the same timestamp
2626
self.ttl_inout.gate_rising(5*us)
@@ -101,28 +101,6 @@ def run(self):
101101
pass
102102

103103

104-
class LoopbackCount(EnvExperiment):
Has a comment. Original line has a comment.
105-
def build(self):
106-
self.setattr_device("core")
107-
self.setattr_device("ttl_inout")
108-
self.setattr_argument("npulses")
109-
110-
def set_count(self, count):
111-
self.set_dataset("count", count)
112-
113-
@kernel
114-
def run(self):
115-
self.ttl_inout.output()
116-
delay(5*us)
117-
with parallel:
118-
self.ttl_inout.gate_rising(10*us)
119-
with sequential:
120-
for i in range(self.npulses):
121-
delay(25*ns)
122-
self.ttl_inout.pulse(25*ns)
123-
self.set_dataset("count", self.ttl_inout.count())
124-
125-
126104
class Underflow(EnvExperiment):
127105
def build(self):
128106
self.setattr_device("core")
@@ -185,17 +163,6 @@ def run(self):
185163

186164

187165
class CoredeviceTest(ExperimentCase):
188-
@unittest.skipUnless(artiq_low_latency,
189-
"timings are dependent on CPU load and network conditions")
190-
def test_rtt(self):
191-
self.execute(RTT)
192-
rtt = self.dataset_mgr.get("rtt")
193-
print(rtt)
194-
self.assertGreater(rtt, 0*ns)
195-
self.assertLess(rtt, 100*ns)
196-
197-
@unittest.skipUnless(artiq_low_latency,
198-
"timings are dependent on CPU load and network conditions")
199166
def test_loopback(self):
200167
self.execute(Loopback)
201168
rtt = self.dataset_mgr.get("rtt")
@@ -208,21 +175,13 @@ def test_clock_generator_loopback(self):
208175
count = self.dataset_mgr.get("count")
209176
self.assertEqual(count, 10)
210177

211-
@unittest.skipUnless(artiq_low_latency,
212-
"timings are dependent on CPU load and network conditions")
213178
def test_pulse_rate(self):
214179
self.execute(PulseRate)
215180
rate = self.dataset_mgr.get("pulse_rate")
216181
print(rate)
217182
self.assertGreater(rate, 100*ns)
218183
self.assertLess(rate, 2500*ns)
219184

220-
def test_loopback_count(self):
221-
npulses = 2
222-
self.execute(LoopbackCount, npulses=npulses)
223-
count = self.dataset_mgr.get("count")
224-
self.assertEqual(count, npulses)
225-
226185
def test_underflow(self):
227186
with self.assertRaises(RTIOUnderflow):
228187
self.execute(Underflow)

‎examples/master/device_db.pyon

-1
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,6 @@
157157
"command": "lda_controller -p {port} --bind {bind} --simulation"
158158
},
159159

160-
"ttl_inout": "pmt0",
161160
"ttl_out": "ttl0",
162161
"ttl_out_serdes": "ttl0",
163162

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