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base repository: m-labs/artiq
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base: e7146cc99942
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head repository: m-labs/artiq
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compare: 312e09150e07
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  • 5 commits
  • 4 files changed
  • 1 contributor

Commits on Feb 27, 2016

  1. gateware.pipistrello: use pmod for spi

    @jordens
    jordens committed Feb 27, 2016
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    ade3eda View commit details

  2. gateware.spi: add complete spi master logic

    @jordens
    jordens committed Feb 27, 2016
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    bd9ceb4 View commit details

Commits on Feb 28, 2016

  1. gateware.spi: refactor, sim verified

    @jordens
    jordens committed Feb 28, 2016
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    3b6999a View commit details

  2. rtio.spi: drop unused argument

    @jordens
    jordens committed Feb 28, 2016
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    f8732ac View commit details

  3. kc705/clock: add spi bus for dac on ams101

    @jordens
    jordens committed Feb 28, 2016
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    312e091 View commit details
Showing with 423 additions and 62 deletions.
  1. +1 −1 artiq/gateware/rtio/phy/spi.py
  2. +397 −49 artiq/gateware/spi.py
  3. +17 −1 artiq/gateware/targets/kc705.py
  4. +8 −11 artiq/gateware/targets/pipistrello.py
2 changes: 1 addition & 1 deletion artiq/gateware/rtio/phy/spi.py
View file
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@


class SPIMaster(Module):
def __init__(self, pads, onehot=False, **kwargs):
def __init__(self, pads, **kwargs):
self.submodules._ll = ClockDomainsRenamer("rio")(
SPIMasterWB(pads, **kwargs))
self.submodules._rt2wb = RT2WB(2, self._ll.bus)
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