m-labs · Mar 3, 2016 · Mar 3, 2016 · Mar 3, 2016
Showing with 34 additions and 29 deletions.

+2 −2 artiq/gateware/nist_clock.py

+1 −1 artiq/gateware/nist_qc2.py

+14 −8 artiq/gateware/soc.py

+15 −8 artiq/gateware/targets/kc705.py

+2 −10 artiq/gateware/targets/pipistrello.py
diff --git a/artiq/gateware/nist_clock.py b/artiq/gateware/nist_clock.py
@@ -38,8 +38,8 @@
         Subsignal("rst", Pins("LPC:LA25_P")),
         IOStandard("LVTTL")),
 
-    ("i2c", 0,
-        Subsignal("scl", Pins("LPC:IIC_SLC")),
+    ("i2c_fmc", 0,
+        Subsignal("scl", Pins("LPC:IIC_SCL")),
         Subsignal("sda", Pins("LPC:IIC_SDA")),
         IOStandard("LVCMOS25")),
 

diff --git a/artiq/gateware/nist_qc2.py b/artiq/gateware/nist_qc2.py
@@ -48,7 +48,7 @@
         Subsignal("rst", Pins("LPC:LA25_P")),
         IOStandard("LVTTL")),
 
-    ("i2c", 0,
+    ("i2c_fmc", 0,
         Subsignal("scl", Pins("LPC:IIC_SCL")),
         Subsignal("sda", Pins("LPC:IIC_SDA")),
         IOStandard("LVCMOS25")),

diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py
@@ -32,11 +32,17 @@ def __init__(self):
                                self.mem_map["mailbox"] | 0x80000000, 4)
 
         self.submodules.timer_kernel = timer.Timer()
-        timer_csrs = self.timer_kernel.get_csrs()
-        timerwb = wishbone.CSRBank(timer_csrs)
-        self.submodules += timerwb
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["timer_kernel"]),
-                                     timerwb.bus)
-        self.add_csr_region("timer_kernel",
-                            self.mem_map["timer_kernel"] | 0x80000000, 32,
-                            timer_csrs)
+        self.register_kernel_cpu_csrdevice("timer_kernel")
+
+    def register_kernel_cpu_csrdevice(self, name):
+        # make sure the device is not getting connected to the comms-CPU already
+        assert self.csr_map[name] is None
+
+        csrs = getattr(self, name).get_csrs()
+        bank = wishbone.CSRBank(csrs)
+        self.submodules += bank
+        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]),
+                                     bank.bus)
+        self.add_csr_region(name,
+                            self.mem_map[name] | 0x80000000, 32,
+                            csrs)
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -134,6 +134,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
     def add_rtio(self, rtio_channels):
         self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
         self.submodules.rtio = rtio.RTIO(rtio_channels)
+        self.register_kernel_cpu_csrdevice("rtio")
         self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
 
@@ -154,13 +155,6 @@ def add_rtio(self, rtio_channels):
             self.ethphy.crg.cd_eth_rx.clk,
             self.ethphy.crg.cd_eth_tx.clk)
 
-        rtio_csrs = self.rtio.get_csrs()
-        self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
-                                     self.rtiowb.bus)
-        self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
-                            rtio_csrs)
-
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
             self.get_native_sdram_if())
 
@@ -297,8 +291,17 @@ def __init__(self, cpu_type="or1k", **kwargs):
 class NIST_QC2(_NIST_Ions):
     """
     NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
-    and 12 DDS channels.  Current implementation for single backplane.  
+    and 12 DDS channels. Current implementation for single backplane.
     """
+    csr_map = {
+        "i2c": None
+    }
+    csr_map.update(_NIST_Ions.csr_map)
+    mem_map = {
+        "i2c":  0x30000000 # (shadow @0xb0000000)
+    }
+    mem_map.update(_NIST_Ions.mem_map)
+
     def __init__(self, cpu_type="or1k", **kwargs):
         _NIST_Ions.__init__(self, cpu_type, **kwargs)
 
@@ -347,6 +350,10 @@ def __init__(self, cpu_type="or1k", **kwargs):
         assert self.rtio.fine_ts_width <= 3
         self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width
 
+        i2c = platform.request("i2c")
+        self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
+        self.register_kernel_cpu_csrdevice("i2c")
+
 
 def main():
     parser = argparse.ArgumentParser(

diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
@@ -209,20 +209,12 @@ def __init__(self, cpu_type="or1k", **kwargs):
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.LogChannel())
 
-        # RTIO core
+        # RTIO logic
         self.submodules.rtio = rtio.RTIO(rtio_channels)
+        self.register_kernel_cpu_csrdevice("rtio")
         self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
         self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
-
-        # CPU connections
-        rtio_csrs = self.rtio.get_csrs()
-        self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
-                                     self.rtiowb.bus)
-        self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
-                            rtio_csrs)
-
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
             self.get_native_sdram_if())