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gateware/nist_clock: pin assignment corrections from David Leibrandt
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sbourdeauducq committed Mar 3, 2016
1 parent d3f36ce commit 0c97043
Showing 1 changed file with 5 additions and 5 deletions.
10 changes: 5 additions & 5 deletions artiq/gateware/nist_clock.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@
("ttl", 4, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
("ttl", 5, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
("ttl", 6, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
("ttl", 7, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
("ttl", 7, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
("ttl", 8, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")),
("ttl", 10, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
@@ -66,9 +66,9 @@
IOStandard("LVTTL")),

("spi", 2,
Subsignal("clk", Pins("LPC:LA27_P")),
Subsignal("cs_n", Pins("LPC:LA26_P")),
Subsignal("mosi", Pins("LPC:LA27_N")),
Subsignal("miso", Pins("LPC:LA26_N")),
Subsignal("clk", Pins("LPC:LA26_N")),
Subsignal("cs_n", Pins("LPC:LA27_N")),
Subsignal("mosi", Pins("LPC:LA26_P")),
Subsignal("miso", Pins("LPC:LA27_P")),
IOStandard("LVTTL")),
]

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