kc705.clock: add all spi buses

m-labs · Mar 3, 2016 · 7ff0c89 · 7ff0c89
1 parent 669fbaa
commit 7ff0c89
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -264,7 +264,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 
-        for i in range(1):  # spi1 and spi2 collide in pinout with ttl
+        for i in range(3):
             phy = spi.SPIMaster(self.platform.request("spi", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(