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base repository: m-labs/misoc
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  • 5 commits
  • 16 files changed
  • 1 contributor

Commits on Mar 5, 2016

  1. interconnect/stream: remove sop support

    @enjoy-digital
    enjoy-digital committed Mar 5, 2016
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    aed8829 View commit details

  2. cores/liteeth_mini: remove use of sop 

    tested on kc705
    @enjoy-digital
    enjoy-digital committed Mar 5, 2016
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    4bf472e View commit details

  3. cores/liteeth_mini/phy: remove with_hw_init_reset parameter 

    with_hw_init_reset is only useful when phys are used without a cpu, liteeth_mini is always used with a cpu.
    @enjoy-digital
    enjoy-digital committed Mar 5, 2016
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    5f124ec View commit details

  4. cores/liteeth_mini/phy: remove loopback phy

    @enjoy-digital
    enjoy-digital committed Mar 5, 2016
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    f874292 View commit details

  5. cores/liteeth_mini/mac: remove frontend/core directories

    @enjoy-digital
    enjoy-digital committed Mar 5, 2016
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    fc1202c View commit details
2 changes: 1 addition & 1 deletion misoc/cores/liteeth_mini/mac/__init__.py
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Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
from misoc.interconnect.csr import *
from misoc.cores.liteeth_mini.common import *
from misoc.cores.liteeth_mini.mac.core import LiteEthMACCore
from misoc.cores.liteeth_mini.mac.frontend.wishbone import LiteEthMACWishboneInterface
from misoc.cores.liteeth_mini.mac.wishbone import LiteEthMACWishboneInterface


class LiteEthMAC(Module, AutoCSR):
2 changes: 1 addition & 1 deletion ...c/cores/liteeth_mini/mac/core/__init__.py → misoc/cores/liteeth_mini/mac/core.py
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Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@

from misoc.interconnect.csr import *
from misoc.cores.liteeth_mini.common import *
from misoc.cores.liteeth_mini.mac.core import gap, preamble, crc, padding, last_be
from misoc.cores.liteeth_mini.mac import gap, preamble, crc, padding, last_be
from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII


5 changes: 2 additions & 3 deletions misoc/cores/liteeth_mini/mac/core/crc.py → misoc/cores/liteeth_mini/mac/crc.py
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Original file line number Diff line number Diff line change
@@ -153,7 +153,7 @@ def __init__(self, crc_class, description):
fsm.act("IDLE",
crc.reset.eq(1),
sink.ack.eq(1),
If(sink.stb & sink.sop,
If(sink.stb,
sink.ack.eq(0),
NextState("COPY"),
)
@@ -251,7 +251,6 @@ def __init__(self, crc_class, description):
self.sink.ack.eq(fifo_in),

source.stb.eq(sink.stb & fifo_full),
source.sop.eq(fifo.source.sop),
source.eop.eq(sink.eop),
fifo.source.ack.eq(fifo_out),
source.payload.eq(fifo.source.payload),
@@ -266,7 +265,7 @@ def __init__(self, crc_class, description):
)
self.comb += crc.data.eq(sink.data)
fsm.act("IDLE",
If(sink.stb & sink.sop & sink.ack,
If(sink.stb & sink.ack,
crc.ce.eq(1),
NextState("COPY")
)
Empty file removed misoc/cores/liteeth_mini/mac/frontend/__init__.py
View file
Empty file.
0 misoc/cores/liteeth_mini/mac/core/gap.py → misoc/cores/liteeth_mini/mac/gap.py
View file
File renamed without changes.
8 changes: 3 additions & 5 deletions misoc/cores/liteeth_mini/mac/core/last_be.py → misoc/cores/liteeth_mini/mac/last_be.py
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Original file line number Diff line number Diff line change
@@ -11,18 +11,17 @@ def __init__(self, dw):

# # #

ongoing = Signal()
ongoing = Signal(reset=1)
self.sync += \
If(sink.stb & sink.ack,
If(sink.sop,
If(sink.eop,
ongoing.eq(1)
).Elif(sink.last_be,
ongoing.eq(0)
)
)
self.comb += [
source.stb.eq(sink.stb & (sink.sop | ongoing)),
source.sop.eq(sink.sop),
source.stb.eq(sink.stb & ongoing),
source.eop.eq(sink.last_be),
source.data.eq(sink.data),
sink.ack.eq(source.ack)
@@ -38,7 +37,6 @@ def __init__(self, dw):

self.comb += [
source.stb.eq(sink.stb),
source.sop.eq(sink.sop),
source.eop.eq(sink.eop),
source.data.eq(sink.data),
source.last_be.eq(sink.eop),
14 changes: 7 additions & 7 deletions misoc/cores/liteeth_mini/mac/core/padding.py → misoc/cores/liteeth_mini/mac/padding.py
View file
Original file line number Diff line number Diff line change
@@ -20,15 +20,11 @@ def __init__(self, dw, padding):
counter_reset = Signal()
counter_ce = Signal()
self.sync += If(counter_reset,
counter.eq(1)
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
self.comb += [
counter_reset.eq(sink.stb & sink.sop & sink.ack),
counter_ce.eq(source.stb & source.ack),
counter_done.eq(counter >= padding_limit),
]
self.comb += counter_done.eq(counter >= padding_limit)

self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
@@ -39,6 +35,8 @@ def __init__(self, dw, padding):
If(~counter_done,
source.eop.eq(0),
NextState("PADDING")
).Else(
counter_reset.eq(1)
)
)
)
@@ -47,8 +45,10 @@ def __init__(self, dw, padding):
source.stb.eq(1),
source.eop.eq(counter_done),
source.data.eq(0),
If(source.ack,
If(source.stb & source.ack,
counter_ce.eq(1),
If(counter_done,
counter_reset.eq(1),
NextState("IDLE")
)
)
20 changes: 2 additions & 18 deletions ...c/cores/liteeth_mini/mac/core/preamble.py → misoc/cores/liteeth_mini/mac/preamble.py
View file
Original file line number Diff line number Diff line change
@@ -32,14 +32,13 @@ def __init__(self, dw):
fsm.act("IDLE",
self.sink.ack.eq(1),
clr_cnt.eq(1),
If(self.sink.stb & self.sink.sop,
If(self.sink.stb,
self.sink.ack.eq(0),
NextState("INSERT"),
)
)
fsm.act("INSERT",
self.source.stb.eq(1),
self.source.sop.eq(cnt == 0),
chooser(preamble, cnt, self.source.data),
If(cnt == cnt_max,
If(self.source.ack, NextState("COPY"))
@@ -54,7 +53,6 @@ def __init__(self, dw):
]
fsm.act("COPY",
self.sink.connect(self.source, leave_out=set(["data", "last_be"])),
self.source.sop.eq(0),

If(self.sink.stb & self.sink.eop & self.source.ack,
NextState("IDLE"),
@@ -93,16 +91,6 @@ def __init__(self, dw):
discard.eq(1)
)

sop = Signal()
clr_sop = Signal()
set_sop = Signal()
self.sync += \
If(clr_sop,
sop.eq(0)
).Elif(set_sop,
sop.eq(1)
)

ref = Signal(dw)
match = Signal()
self.comb += [
@@ -117,7 +105,7 @@ def __init__(self, dw):
self.sink.ack.eq(1),
clr_cnt.eq(1),
clr_discard.eq(1),
If(self.sink.stb & self.sink.sop,
If(self.sink.stb,
clr_cnt.eq(0),
inc_cnt.eq(1),
clr_discard.eq(0),
@@ -133,7 +121,6 @@ def __init__(self, dw):
If(discard | (~match),
NextState("IDLE")
).Else(
set_sop.eq(1),
NextState("COPY")
)
).Else(
@@ -147,9 +134,6 @@ def __init__(self, dw):
]
fsm.act("COPY",
self.sink.connect(self.source, leave_out=set(["data", "last_be"])),
self.source.sop.eq(sop),
clr_sop.eq(self.source.stb & self.source.ack),

If(self.source.stb & self.source.eop & self.source.ack,
NextState("IDLE"),
)
13 changes: 2 additions & 11 deletions ...c/cores/liteeth_mini/mac/frontend/sram.py → misoc/cores/liteeth_mini/mac/sram.py
View file
Original file line number Diff line number Diff line change
@@ -64,7 +64,7 @@ def __init__(self, dw, depth, nslots=2):
self.submodules += fsm

fsm.act("IDLE",
If(sink.stb & sink.sop,
If(sink.stb,
If(fifo.sink.ack,
ongoing.eq(1),
counter_ce.eq(1),
@@ -166,7 +166,6 @@ def __init__(self, dw, depth, nslots=2):


# fsm
first = Signal()
last = Signal()
last_d = Signal()

@@ -202,7 +201,6 @@ def __init__(self, dw, depth, nslots=2):
]
fsm.act("SEND",
source.stb.eq(1),
source.sop.eq(first),
source.eop.eq(last),
If(source.ack,
counter_ce.eq(~last),
@@ -215,14 +213,7 @@ def __init__(self, dw, depth, nslots=2):
NextState("IDLE")
)

# first/last computation
self.sync += [
If(fsm.ongoing("IDLE"),
first.eq(1)
).Elif(source.stb & source.ack,
first.eq(0)
)
]
# last computation
self.comb += last.eq((counter + 4) >= fifo.source.length)
self.sync += last_d.eq(last)

2 changes: 1 addition & 1 deletion ...res/liteeth_mini/mac/frontend/wishbone.py → misoc/cores/liteeth_mini/mac/wishbone.py
View file
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@
from misoc.interconnect.csr import *
from misoc.interconnect.stream import *
from misoc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
from misoc.cores.liteeth_mini.mac.frontend import sram
from misoc.cores.liteeth_mini.mac import sram


class LiteEthMACWishboneInterface(Module, AutoCSR):
32 changes: 6 additions & 26 deletions misoc/cores/liteeth_mini/phy/gmii.py
View file
Original file line number Diff line number Diff line change
@@ -31,24 +31,16 @@ def __init__(self, pads):
# # #

dv_d = Signal()
self.sync += dv_d.eq(pads.dv)

sop = Signal()
eop = Signal()
self.comb += [
sop.eq(pads.dv & ~dv_d),
eop.eq(~pads.dv & dv_d)
]
self.sync += [
dv_d.eq(pads.dv),
source.stb.eq(pads.dv),
source.sop.eq(sop),
source.data.eq(pads.rx_data)
]
self.comb += source.eop.eq(eop)
self.comb += source.eop.eq(~pads.dv & dv_d)


class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
def __init__(self, clock_pads, pads, mii_mode=0):
self._reset = CSRStorage()

# # #
@@ -69,19 +61,7 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
i_S=mii_mode,
o_O=self.cd_eth_tx.clk)

if with_hw_init_reset:
reset = Signal()
counter = Signal(max=512)
counter_done = Signal()
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
else:
reset = self._reset.storage
reset = self._reset.storage
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
@@ -90,9 +70,9 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):


class LiteEthPHYGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
def __init__(self, clock_pads, pads):
self.dw = 8
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source
4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/phy/gmii_mii.py
View file
Original file line number Diff line number Diff line change
@@ -159,12 +159,12 @@ def __init__(self, clk_freq):


class LiteEthPHYGMIIMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
def __init__(self, clock_pads, pads, clk_freq):
self.dw = 8
# Note: we can use GMII CRG since it also handles tx clock pad used for MII
self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
mode = self.mode_detection.mode
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, mode == modes["MII"])
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIIMIITX(pads, mode))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIMIIRX(pads, mode))
self.sink, self.source = self.tx.sink, self.rx.source
35 changes: 0 additions & 35 deletions misoc/cores/liteeth_mini/phy/loopback.py
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