m-labs · Mar 5, 2016 · Mar 5, 2016 · Mar 5, 2016 · Mar 5, 2016 · Mar 5, 2016
diff --git a/misoc/cores/dvi_sampler/analysis.py b/misoc/cores/dvi_sampler/analysis.py
@@ -4,6 +4,7 @@
 from migen.genlib.record import Record
 
 from misoc.interconnect.csr import *
+from misoc.interconnect import stream
 from misoc.cores.dvi_sampler.common import channel_layout
 
 
@@ -119,7 +120,7 @@ def __init__(self, word_width, fifo_depth):
 
         # in sys clock domain
         word_layout = [("sof", 1), ("pixels", word_width)]
-        self.frame = Source(word_layout)
+        self.frame = stream.Endpoint(word_layout)
         self.busy = Signal()
 
         self._overflow = CSR()

diff --git a/misoc/cores/dvi_sampler/dma.py b/misoc/cores/dvi_sampler/dma.py
@@ -3,6 +3,7 @@
 
 from misoc.interconnect.csr import *
 from misoc.interconnect.csr_eventmanager import *
+from misoc.interconnect import stream
 
 # TODO: rewrite dma_lasmi module
 # TODO: use stream packets to resync DMA
@@ -70,7 +71,7 @@ def __init__(self, lasmim, nslots):
         alignment_bits = bits_for(bus_dw//8) - 1
 
         fifo_word_width = 24*bus_dw//32
-        self.frame = Sink([("sof", 1), ("pixels", fifo_word_width)])
+        self.frame = stream.Endpoint([("sof", 1), ("pixels", fifo_word_width)])
         self._frame_size = CSRStorage(bus_aw + alignment_bits, alignment_bits=alignment_bits)
         self.submodules._slot_array = _SlotArray(nslots, bus_aw, alignment_bits)
         self.ev = self._slot_array.ev

diff --git a/misoc/cores/framebuffer/format.py b/misoc/cores/framebuffer/format.py
@@ -5,6 +5,8 @@
 from migen.genlib.fsm import FSM, NextState
 from migen.actorlib import spi
 
+from misoc.interconnect import stream
+
 _hbits = 12
 _vbits = 12
 
@@ -77,9 +79,9 @@ def __init__(self, pack_factor):
             ("vsync_start", _vbits),
             ("vsync_end", _vbits),
             ("vscan", _vbits)]
-        self.timing = Sink(timing_layout)
-        self.pixels = Sink(pixel_layout(pack_factor))
-        self.phy = Source(phy_layout(pack_factor))
+        self.timing = stream.Endpoint(timing_layout)
+        self.pixels = stream.Endpoint(pixel_layout(pack_factor))
+        self.phy = stream.Endpoint(phy_layout(pack_factor))
         self.busy = Signal()
 
         ###

diff --git a/misoc/cores/framebuffer/phy.py b/misoc/cores/framebuffer/phy.py
@@ -6,11 +6,12 @@
 
 from misoc.framebuffer.format import bpc_phy, phy_layout
 from misoc.framebuffer import dvi
+from misoc.interconnect import stream
 
 
 class _FIFO(Module):
     def __init__(self, pack_factor):
-        self.phy = Sink(phy_layout(pack_factor))
+        self.phy = stream.Endpoint(phy_layout(pack_factor))
         self.busy = Signal()
 
         self.pix_hsync = Signal()

diff --git a/misoc/cores/liteeth_mini/common.py b/misoc/cores/liteeth_mini/common.py
@@ -1,17 +1,4 @@
 from migen import *
-from migen.genlib.record import *
-
-from misoc.interconnect.csr import *
-from misoc.interconnect.stream import *
-
-
-class Port:
-    def connect(self, port):
-        r = [
-            self.source.connect(port.sink),
-            port.source.connect(self.sink)
-        ]
-        return r
 
 eth_mtu = 1532
 eth_min_len = 46
@@ -21,18 +8,15 @@ def connect(self, port):
 
 
 def eth_phy_description(dw):
-    payload_layout = [
+    return [
         ("data", dw),
         ("last_be", dw//8),
         ("error", dw//8)
     ]
-    return EndpointDescription(payload_layout, packetized=True)
-
 
 def eth_mac_description(dw):
-    payload_layout = mac_header.get_layout() + [
+    return mac_header.get_layout() + [
         ("data", dw),
         ("last_be", dw//8),
         ("error", dw//8)
     ]
-    return EndpointDescription(payload_layout, packetized=True)
diff --git a/misoc/cores/liteeth_mini/mac/__init__.py b/misoc/cores/liteeth_mini/mac/__init__.py
@@ -15,7 +15,10 @@ def __init__(self, phy, dw,
         self.csrs = []
         if interface == "wishbone":
             self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
-            self.comb += Port.connect(self.interface, self.core)
+            self.comb += [
+                self.interface.source.connect(self.core.sink),
+                self.core.source.connect(self.interface.sink)
+            ]
             self.ev, self.bus = self.interface.sram.ev, self.interface.bus
             self.csrs = self.interface.get_csrs() + self.core.get_csrs()
         else:

diff --git a/misoc/cores/liteeth_mini/mac/core.py b/misoc/cores/liteeth_mini/mac/core.py
@@ -1,6 +1,7 @@
 from migen import *
 
 from misoc.interconnect.csr import *
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import *
 from misoc.cores.liteeth_mini.mac import gap, preamble, crc, padding, last_be
 from misoc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
@@ -66,10 +67,10 @@ def __init__(self, phy, dw, endianness="big",
         # Converters
         if dw != phy.dw:
             reverse = endianness == "big"
-            tx_converter = Converter(eth_phy_description(dw),
+            tx_converter = stream.Converter(eth_phy_description(dw),
                                      eth_phy_description(phy.dw),
                                      reverse=reverse)
-            rx_converter = Converter(eth_phy_description(phy.dw),
+            rx_converter = stream.Converter(eth_phy_description(phy.dw),
                                      eth_phy_description(dw),
                                      reverse=reverse)
             self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
@@ -83,8 +84,8 @@ def __init__(self, phy, dw, endianness="big",
             fifo_depth = 8
         else:
             fifo_depth = 64
-        tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
-        rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
+        tx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
+        rx_cdc = stream.AsyncFIFO(eth_phy_description(dw), fifo_depth)
         self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
         self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
 

diff --git a/misoc/cores/liteeth_mini/mac/crc.py b/misoc/cores/liteeth_mini/mac/crc.py
@@ -5,7 +5,7 @@
 from migen import *
 from migen.genlib.misc import chooser
 
-from misoc.interconnect.stream import *
+from misoc.interconnect import stream
 
 
 class LiteEthMACCRCEngine(Module):
@@ -139,9 +139,8 @@ class LiteEthMACCRCInserter(Module):
         Packets output with CRC.
     """
     def __init__(self, crc_class, description):
-        self.sink = sink = Sink(description)
-        self.source = source = Source(description)
-        self.busy = Signal()
+        self.sink = sink = stream.Endpoint(description)
+        self.source = source = stream.Endpoint(description)
 
         # # #
 
@@ -193,7 +192,6 @@ def __init__(self, crc_class, description):
                 source.data.eq(crc.value),
                 If(source.ack, NextState("IDLE"))
             )
-        self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
 
 
 class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
@@ -220,9 +218,8 @@ class LiteEthMACCRCChecker(Module):
         on eop when CRC OK / set to 1 when CRC KO.
     """
     def __init__(self, crc_class, description):
-        self.sink = sink = Sink(description)
-        self.source = source = Source(description)
-        self.busy = Signal()
+        self.sink = sink = stream.Endpoint(description)
+        self.source = source = stream.Endpoint(description)
 
         # # #
 
@@ -231,7 +228,7 @@ def __init__(self, crc_class, description):
         self.submodules += crc
         ratio = crc.width//dw
 
-        fifo = ResetInserter()(SyncFIFO(description, ratio + 1))
+        fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
         self.submodules += fifo
 
         fsm = FSM(reset_state="RESET")
@@ -278,7 +275,6 @@ def __init__(self, crc_class, description):
                 )
             )
         )
-        self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
 
 
 class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):

diff --git a/misoc/cores/liteeth_mini/mac/gap.py b/misoc/cores/liteeth_mini/mac/gap.py
@@ -3,14 +3,14 @@
 from migen import *
 from migen.genlib.fsm import *
 
-from misoc.interconnect.stream import Sink, Source
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
 
 
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):
-        self.sink = sink = Sink(eth_phy_description(dw))
-        self.source = source = Source(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/last_be.py b/misoc/cores/liteeth_mini/mac/last_be.py
@@ -1,13 +1,13 @@
 from migen import *
 
-from misoc.interconnect.stream import *
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import eth_phy_description
 
 
 class LiteEthMACTXLastBE(Module):
     def __init__(self, dw):
-        self.sink = sink = Sink(eth_phy_description(dw))
-        self.source = source = Source(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 
@@ -30,8 +30,8 @@ def __init__(self, dw):
 
 class LiteEthMACRXLastBE(Module):
     def __init__(self, dw):
-        self.sink = sink = Sink(eth_phy_description(dw))
-        self.source = source = Source(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/padding.py b/misoc/cores/liteeth_mini/mac/padding.py
@@ -2,14 +2,14 @@
 
 from migen import *
 
-from misoc.interconnect.stream import *
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import eth_phy_description
 
 
 class LiteEthMACPaddingInserter(Module):
     def __init__(self, dw, padding):
-        self.sink = sink = Sink(eth_phy_description(dw))
-        self.source = source = Source(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 
@@ -57,8 +57,8 @@ def __init__(self, dw, padding):
 
 class LiteEthMACPaddingChecker(Module):
     def __init__(self, dw, packet_min_length):
-        self.sink = sink = Sink(eth_phy_description(dw))
-        self.source = source = Source(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/preamble.py b/misoc/cores/liteeth_mini/mac/preamble.py
@@ -3,14 +3,14 @@
 from migen.genlib.misc import chooser
 from migen.genlib.record import Record
 
-from misoc.interconnect.stream import *
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
 
 
 class LiteEthMACPreambleInserter(Module):
     def __init__(self, dw):
-        self.sink = Sink(eth_phy_description(dw))
-        self.source = Source(eth_phy_description(dw))
+        self.sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 
@@ -62,8 +62,8 @@ def __init__(self, dw):
 
 class LiteEthMACPreambleChecker(Module):
     def __init__(self, dw):
-        self.sink = Sink(eth_phy_description(dw))
-        self.source = Source(eth_phy_description(dw))
+        self.sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = stream.Endpoint(eth_phy_description(dw))
 
         # # #
 

diff --git a/misoc/cores/liteeth_mini/mac/sram.py b/misoc/cores/liteeth_mini/mac/sram.py
@@ -2,14 +2,13 @@
 
 from misoc.interconnect.csr import *
 from misoc.interconnect.csr_eventmanager import *
-from misoc.interconnect.stream import *
-
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import eth_phy_description
 
 
 class LiteEthMACSRAMWriter(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2):
-        self.sink = sink = Sink(eth_phy_description(dw))
+        self.sink = sink = stream.Endpoint(eth_phy_description(dw))
         self.crc_error = Signal()
 
         slotbits = max(log2_int(nslots), 1)
@@ -56,7 +55,7 @@ def __init__(self, dw, depth, nslots=2):
         ongoing = Signal()
 
         # status fifo
-        fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
+        fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
         self.submodules += fifo
 
         # fsm
@@ -127,7 +126,7 @@ def __init__(self, dw, depth, nslots=2):
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2):
-        self.source = source = Source(eth_phy_description(dw))
+        self.source = source = stream.Endpoint(eth_phy_description(dw))
 
         slotbits = max(log2_int(nslots), 1)
         lengthbits = log2_int(depth*4)  # length in bytes
@@ -145,7 +144,7 @@ def __init__(self, dw, depth, nslots=2):
         # # #
 
         # command fifo
-        fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
+        fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
         self.submodules += fifo
         self.comb += [
             fifo.sink.stb.eq(self._start.re),

diff --git a/misoc/cores/liteeth_mini/mac/wishbone.py b/misoc/cores/liteeth_mini/mac/wishbone.py
@@ -3,15 +3,15 @@
 
 from misoc.interconnect import wishbone
 from misoc.interconnect.csr import *
-from misoc.interconnect.stream import *
+from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
 from misoc.cores.liteeth_mini.mac import sram
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):
     def __init__(self, dw, nrxslots=2, ntxslots=2):
-        self.sink = Sink(eth_phy_description(dw))
-        self.source = Source(eth_phy_description(dw))
+        self.sink = stream.Endpoint(eth_phy_description(dw))
+        self.source = stream.Endpoint(eth_phy_description(dw))
         self.bus = wishbone.Interface()
 
         # # #