sim: add more signals to VCD (#36)

m-labs · Mar 2, 2016 · ba8f576 · ba8f576
1 parent bc21743
commit ba8f576
Showing 2 changed files with 14 additions and 6 deletions.
diff --git a/migen/sim/core.py b/migen/sim/core.py
@@ -8,7 +8,8 @@
                                   _Operator, _Slice, _ArrayProxy,
                                   _Assign, _Fragment)
 from migen.fhdl.bitcontainer import value_bits_sign
-from migen.fhdl.tools import list_targets, insert_resets, lower_specials
+from migen.fhdl.tools import (list_targets, list_signals,
+                              insert_resets, lower_specials)
 from migen.fhdl.simplify import MemoryToArray
 from migen.fhdl.specials import _MemoryLocation
 from migen.sim.vcd import VCDWriter, DummyVCDWriter
@@ -264,6 +265,16 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
         else:
             self.vcd = VCDWriter(vcd_name)
 
+            signals = list_signals(self.fragment)
+            for cd in self.fragment.clock_domains:
+                signals.add(cd.clk)
+                if cd.rst is not None:
+                    signals.add(cd.rst)
+            for memory_array in mta.replacements.values():
+                signals |= set(memory_array)
+            for signal in sorted(signals, key=lambda x: x.duid):
+                self.vcd.set(signal, signal.reset.value)
+
     def __enter__(self):
         return self
 

diff --git a/migen/sim/vcd.py b/migen/sim/vcd.py
@@ -44,11 +44,8 @@ def _write_value(self, f, signal, value):
         f.write(fmtstr.format(value, code))
 
     def set(self, signal, value):
-        if signal in self.signal_values:
-            write = self.signal_values[signal] != value
-        else:
-            write = signal.reset.value != value
-        if write:
+        if (signal not in self.signal_values
+                or self.signal_values[signal] != value):
             self._write_value(self.buffer_file, signal, value)
             self.signal_values[signal] = value