m-labs · Feb 29, 2016 · Feb 29, 2016 · Feb 29, 2016 · Feb 29, 2016 · Feb 29, 2016
diff --git a/artiq/coredevice/rt2wb.py b/artiq/coredevice/rt2wb.py
@@ -3,12 +3,16 @@
 
 
 @syscall
-def rt2wb_write(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
-                ) -> TNone:
+def rt2wb_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
+                 ) -> TNone:
     raise NotImplementedError("syscall not simulated")
 
 
 @syscall
-def rt2wb_read_sync(time_mu: TInt64, channel: TInt32, addr: TInt32,
-                    duration_mu: TInt32) -> TInt32:
+def rt2wb_input(channel: TInt32) -> TInt32:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall
+def rt2wb_input_sync(timeout_mu: TInt64, channel: TInt32) -> TInt32:
     raise NotImplementedError("syscall not simulated")
diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py
@@ -1,7 +1,7 @@
 from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
-                                 delay_mu)
+                                 delay_mu, int)
 from artiq.language.units import MHz
-from artiq.coredevice.rt2wb import rt2wb_write, rt2wb_read_sync
+from artiq.coredevice.rt2wb import rt2wb_output, rt2wb_input, rt2wb_input_sync
 
 
 SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
@@ -28,11 +28,11 @@ class SPIMaster:
     def __init__(self, dmgr, ref_period, channel):
         self.core = dmgr.get("core")
         self.ref_period = ref_period
-        self.ref_period_mu = seconds_to_mu(ref_period, self.core)
+        self.ref_period_mu = int(seconds_to_mu(ref_period, self.core))
         self.channel = channel
-        self.write_period_mu = 0
-        self.read_period_mu = 0
-        self.xfer_period_mu = 0
+        self.write_period_mu = int(0)
+        self.read_period_mu = int(0)
+        self.xfer_period_mu = int(0)
         # A full transfer takes write_period_mu + xfer_period_mu.
         # Chained transfers can happen every xfer_period_mu.
         # The second transfer of a chain can be written 2*ref_period_mu
@@ -49,11 +49,11 @@ def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
 
     @kernel
     def set_config_mu(self, flags=0, write_div=6, read_div=6):
-        rt2wb_write(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
-                    ((write_div - 2) << 16) | ((read_div - 2) << 24))
+        rt2wb_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
+                     ((write_div - 2) << 16) | ((read_div - 2) << 24))
         self.write_period_mu = int(write_div*self.ref_period_mu)
         self.read_period_mu = int(read_div*self.ref_period_mu)
-        delay_mu(2*self.ref_period_mu)
+        delay_mu(3*self.ref_period_mu)
 
     @portable
     def get_xfer_period_mu(self, write_length, read_length):
@@ -62,33 +62,40 @@ def get_xfer_period_mu(self, write_length, read_length):
 
     @kernel
     def set_xfer(self, chip_select=0, write_length=0, read_length=0):
-        rt2wb_write(now_mu(), self.channel, SPI_XFER_ADDR,
-                    chip_select | (write_length << 16) | (read_length << 24))
-        self.xfer_period_mu = self.get_xfer_period_mu(
-            write_length, read_length)
-        delay_mu(int(2*self.ref_period_mu))
+        rt2wb_output(now_mu(), self.channel, SPI_XFER_ADDR,
+                     chip_select | (write_length << 16) | (read_length << 24))
+        self.xfer_period_mu = self.get_xfer_period_mu(write_length,
+                                                      read_length)
+        delay_mu(3*self.ref_period_mu)
 
     @kernel
     def write(self, data):
-        rt2wb_write(now_mu(), self.channel, SPI_DATA_ADDR, data)
-        delay_mu(int(self.write_period_mu + self.xfer_period_mu))
+        rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
+        delay_mu(3*self.ref_period_mu)
 
     @kernel
-    def read_async(self):
-        rt2wb_write(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
-        delay_mu(int(2*self.ref_period_mu))
+    def read(self):
+        rt2wb_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
+        delay_mu(3*self.ref_period_mu)
+
+    @kernel
+    def input(self):
+        return rt2wb_input(self.channel)
+
+    @kernel
+    def _rt2wb_read_sync(self, addr=0):
+        t = now_mu()
+        rt2wb_output(t, self.channel, addr | SPI_RT2WB_READ, 0)
+        return rt2wb_input_sync(t + 3*self.ref_period_mu, self.channel)
 
     @kernel
     def read_sync(self):
-        return rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
-                               SPI_RT2WB_READ, int(2*self.ref_period_mu))
+        return self._rt2wb_read_sync(SPI_DATA_ADDR)
 
     @kernel
     def _get_config_sync(self):
-        return rt2wb_read_sync(now_mu(), self.channel, SPI_CONFIG_ADDR |
-                               SPI_RT2WB_READ, int(2*self.ref_period_mu))
+        return self._rt2wb_read_sync(SPI_CONFIG_ADDR)
 
     @kernel
     def _get_xfer_sync(self):
-        return rt2wb_read_sync(now_mu(), self.channel, SPI_XFER_ADDR |
-                               SPI_RT2WB_READ, int(2*self.ref_period_mu))
+        return self._rt2wb_read_sync(SPI_XFER_ADDR)
diff --git a/artiq/gateware/nist_clock.py b/artiq/gateware/nist_clock.py
@@ -53,21 +53,21 @@
 
     ("spi", 0,
         Subsignal("clk", Pins("LPC:LA13_N")),
-        Subsignal("ce", Pins("LPC:LA14_N")),
+        Subsignal("cs_n", Pins("LPC:LA14_N")),
         Subsignal("mosi", Pins("LPC:LA17_CC_P")),
         Subsignal("miso", Pins("LPC:LA17_CC_N")),
         IOStandard("LVTTL")),
 
     ("spi", 1,
         Subsignal("clk", Pins("LPC:LA23_N")),
-        Subsignal("ce", Pins("LPC:LA23_P")),
+        Subsignal("cs_n", Pins("LPC:LA23_P")),
         Subsignal("mosi", Pins("LPC:LA18_CC_N")),
         Subsignal("miso", Pins("LPC:LA18_CC_P")),
         IOStandard("LVTTL")),
 
     ("spi", 2,
         Subsignal("clk", Pins("LPC:LA27_P")),
-        Subsignal("ce", Pins("LPC:LA26_P")),
+        Subsignal("cs_n", Pins("LPC:LA26_P")),
         Subsignal("mosi", Pins("LPC:LA27_N")),
         Subsignal("miso", Pins("LPC:LA26_N")),
         IOStandard("LVTTL")),

diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py
@@ -292,14 +292,12 @@ def __init__(self, pads, bus=None, data_width=32):
             data_width, clock_width=len(config.div_read),
             bits_width=len(xfer.read_length))
 
-        wb_we = Signal()
         pending = Signal()
         cs = Signal.like(xfer.cs)
         data_read = Signal.like(spi.reg.data)
         data_write = Signal.like(spi.reg.data)
 
         self.comb += [
-            wb_we.eq(bus.cyc & bus.stb & bus.we & (~pending | spi.done)),
             bus.dat_r.eq(
                 Array([data_read, xfer.raw_bits(), config.raw_bits()
                        ])[bus.adr]),
@@ -310,13 +308,6 @@ def __init__(self, pads, bus=None, data_width=32):
             spi.div_read.eq(config.div_read),
         ]
         self.sync += [
-            bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
-            If(wb_we,
-               Array([data_write, xfer.raw_bits(), config.raw_bits()
-                      ])[bus.adr].eq(bus.dat_w)
-            ),
-            config.active.eq(spi.cs),
-            config.pending.eq(pending),
             If(spi.done,
                 data_read.eq(spi.reg.data),
             ),
@@ -327,9 +318,19 @@ def __init__(self, pads, bus=None, data_width=32):
                 spi.reg.data.eq(data_write),
                 pending.eq(0),
             ),
-            If(wb_we & (bus.adr == 0),  # data register
-                pending.eq(1),
+            bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
+            If(bus.ack,
+                bus.ack.eq(0),
+            ),
+            If(bus.we & bus.ack,
+                Array([data_write, xfer.raw_bits(), config.raw_bits()
+                      ])[bus.adr].eq(bus.dat_w),
+                If(bus.adr == 0,  # data register
+                    pending.eq(1),
+                ),
             ),
+            config.active.eq(spi.cs),
+            config.pending.eq(pending),
         ]
 
         # I/O

diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -250,18 +250,24 @@ def __init__(self, cpu_type="or1k", **kwargs):
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
 
-        spi_pins = self.platform.request("ams101_dac", 0)
-        phy = ttl_simple.Output(spi_pins.ldac)
+        ams101_dac = self.platform.request("ams101_dac", 0)
+        phy = ttl_simple.Output(ams101_dac.ldac)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))
         self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
 
-        phy = spi.SPIMaster(spi_pins)
+        phy = spi.SPIMaster(ams101_dac)
         self.submodules += phy
         self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 
+        for i in range(3):
+            phy = spi.SPIMaster(self.platform.request("spi", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(
+                phy, ofifo_depth=128, ififo_depth=128))
+
         phy = ttl_simple.ClockGen(platform.request("la32_p"))
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy))

diff --git a/artiq/runtime/dds.c b/artiq/runtime/dds.c
@@ -26,7 +26,7 @@
 #endif
 
 #define DDS_WRITE(addr, data) do { \
-        rt2wb_write(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
+        rt2wb_output(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
         now += DURATION_WRITE; \
     } while(0)
 

diff --git a/artiq/runtime/ksupport.c b/artiq/runtime/ksupport.c
@@ -122,8 +122,9 @@ static const struct symbol runtime_exports[] = {
     {"dds_batch_exit", &dds_batch_exit},
     {"dds_set", &dds_set},
 
-    {"rt2wb_write", &rt2wb_write},
-    {"rt2wb_read_sync", &rt2wb_read_sync},
+    {"rt2wb_output", &rt2wb_output},
+    {"rt2wb_input", &rt2wb_input},
+    {"rt2wb_input_sync", &rt2wb_input_sync},
 
     {"cache_get", &cache_get},
     {"cache_put", &cache_put},

diff --git a/artiq/runtime/rt2wb.c b/artiq/runtime/rt2wb.c
@@ -5,29 +5,50 @@
 #include "rt2wb.h"
 
 
-void rt2wb_write(long long int timestamp, int channel, int addr,
+void rt2wb_output(long long int timestamp, int channel, int addr,
         unsigned int data)
 {
     rtio_output(timestamp, channel, addr, data);
 }
 
 
-unsigned int rt2wb_read_sync(long long int timestamp, int channel, int addr,
-        int duration)
+unsigned int rt2wb_input(int channel)
 {
     unsigned int data;
     int status;
 
-    rtio_output(timestamp, channel, addr, 0);
+    rtio_chan_sel_write(channel);
+    status = rtio_i_status_read();
+    if (status & RTIO_I_STATUS_OVERFLOW) {
+        rtio_i_overflow_reset_write(1);
+        artiq_raise_from_c("RTIOOverflow",
+                "RT2WB input overflow on channel {0}",
+                channel, 0, 0);
+    }
+    if (status & RTIO_I_STATUS_EMPTY)
+        artiq_raise_from_c("RTIOTimeout",
+                "RT2WB input timeout on channel {0}",
+                channel, 0, 0);
+
+    data = rtio_i_data_read();
+    rtio_i_re_write(1);
+    return data;
+}
+
+
+unsigned int rt2wb_input_sync(long long int timeout, int channel)
+{
+    unsigned int data;
+    int status;
 
-    status = rtio_input_wait(timestamp + duration, channel);
+    status = rtio_input_wait(timeout, channel);
     if (status & RTIO_I_STATUS_OVERFLOW)
         artiq_raise_from_c("RTIOOverflow",
-                "RT2WB read overflow on channel {0}",
+                "RT2WB input overflow on channel {0}",
                 channel, 0, 0);
     if (status & RTIO_I_STATUS_EMPTY)
         artiq_raise_from_c("RTIOTimeout",
-                "RT2WB read timeout on channel {0}",
+                "RT2WB input timeout on channel {0}",
                 channel, 0, 0);
 
     data = rtio_i_data_read();

diff --git a/artiq/runtime/rt2wb.h b/artiq/runtime/rt2wb.h
@@ -3,10 +3,10 @@
 
 #include "rtio.h"
 
-void rt2wb_write(long long int timestamp, int channel, int address,
+void rt2wb_output(long long int timestamp, int channel, int addr,
 		unsigned int data);
-unsigned int rt2wb_read_sync(long long int timestamp, int channel, int address,
-		int duration);
+unsigned int rt2wb_input(int channel);
+unsigned int rt2wb_input_sync(long long int timeout, int channel);
 
 #endif /* __RT2WB_H */
 
diff --git a/examples/master/device_db.pyon b/examples/master/device_db.pyon
@@ -74,19 +74,50 @@
         "class": "TTLInOut",
         "arguments": {"channel": 18}
     },
-    "ttl_clock_la32_p": {
+    "led": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
-        "class": "TTLClockGen",
+        "class": "TTLOut",
+        "arguments": {"channel": 19}
+    },
+
+    "ams101_ldac": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
         "arguments": {"channel": 20}
     },
+    "ams101_spi": {
+        "type": "local",
+        "module": "artiq.coredevice.spi",
+        "class": "SPIMaster",
+        "arguments": {"channel": 21}
+    },
 
+    "spi0": {
+        "type": "local",
+        "module": "artiq.coredevice.spi",
+        "class": "SPIMaster",
+        "arguments": {"channel": 22}
+    },
+    "spi1": {
+        "type": "local",
+        "module": "artiq.coredevice.spi",
+        "class": "SPIMaster",
+        "arguments": {"channel": 23}
+    },
+    "spi2": {
+        "type": "local",
+        "module": "artiq.coredevice.spi",
+        "class": "SPIMaster",
+        "arguments": {"channel": 24}
+    },
 
-    "led": {
+    "ttl_clock_la32_p": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 19}
+        "class": "TTLClockGen",
+        "arguments": {"channel": 25}
     },
 
     "dds_bus": {