nist_clock: disable spi1/2

m-labs · Mar 1, 2016 · f2ec869 · f2ec869
1 parent 7d7a710
commit f2ec869
Showing 2 changed files with 2 additions and 14 deletions.
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
@@ -262,7 +262,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 
-        for i in range(3):
+        for i in range(1):  # spi1 and spi2 collide in pinout with ttl
             phy = spi.SPIMaster(self.platform.request("spi", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(

diff --git a/examples/master/device_db.pyon b/examples/master/device_db.pyon
@@ -100,24 +100,12 @@
         "class": "SPIMaster",
         "arguments": {"channel": 22}
     },
-    "spi1": {
-        "type": "local",
-        "module": "artiq.coredevice.spi",
-        "class": "SPIMaster",
-        "arguments": {"channel": 23}
-    },
-    "spi2": {
-        "type": "local",
-        "module": "artiq.coredevice.spi",
-        "class": "SPIMaster",
-        "arguments": {"channel": 24}
-    },
 
     "ttl_clock_la32_p": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
         "class": "TTLClockGen",
-        "arguments": {"channel": 25}
+        "arguments": {"channel": 23}
     },
 
     "dds_bus": {