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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: d3f36ce78452
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 2, 2016

  1. ad53xx: ldac may be none

    @jordens
    jordens committed Mar 2, 2016
    Copy the full SHA
    9969cd8 View commit details

  2. kc705: add false paths for ethernet phy 

    * vivado prefers rsys_clk over sys_clk (despite the assignment hierarchy)
  (We need DONT_TOUCH and/or KEEP verilog annotations to fix this)
    @jordens
    jordens committed Mar 2, 2016
    3
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    d3f36ce View commit details
Showing with 19 additions and 16 deletions.
  1. +2 −2 artiq/coredevice/ad53xx.py
  2. +17 −14 artiq/gateware/targets/kc705.py
4 changes: 2 additions & 2 deletions artiq/coredevice/ad53xx.py
View file
Original file line number Diff line number Diff line change
@@ -41,8 +41,8 @@ def __init__(self, dmgr, spi_bus, ldac=None,
chip_select=0, write_div=4, read_div=6):
self.core = dmgr.get("core")
self.bus = dmgr.get(spi_bus)
# if ldac is not None:
ldac = dmgr.get(ldac)
if ldac is not None:
ldac = dmgr.get(ldac)
self.ldac = ldac
self.chip_select = chip_select
self.write_div = write_div
31 changes: 17 additions & 14 deletions artiq/gateware/targets/kc705.py
View file
Original file line number Diff line number Diff line change
@@ -9,6 +9,7 @@
from migen.build.generic_platform import *
from migen.build.xilinx.vivado import XilinxVivadoToolchain
from migen.build.xilinx.ise import XilinxISEToolchain
from migen.fhdl.specials import Keep

from misoc.interconnect.csr import *
from misoc.interconnect import wishbone
@@ -135,20 +136,22 @@ def add_rtio(self, rtio_channels):
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)

if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
self.platform.add_platform_command("""
create_clock -name rsys_clk -period 8.0 [get_nets {rsys_clk}]
create_clock -name rio_clk -period 8.0 [get_nets {rio_clk}]
set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
if isinstance(self.platform.toolchain, XilinxISEToolchain):
self.platform.add_platform_command("""
NET "sys_clk" TNM_NET = "GRPrsys_clk";
NET "{rio_clk}" TNM_NET = "GRPrio_clk";
TIMESPEC "TSfix_cdc1" = FROM "GRPrsys_clk" TO "GRPrio_clk" TIG;
TIMESPEC "TSfix_cdc2" = FROM "GRPrio_clk" TO "GRPrsys_clk" TIG;
""", rio_clk=self.rtio_crg.cd_rtio.clk)
self.specials += [
Keep(self.rtio.cd_rsys.clk),
Keep(self.rtio_crg.cd_rtio.clk),
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk),
]

self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
self.platform.add_false_path_constraints(
self.rtio.cd_rsys.clk,
self.rtio_crg.cd_rtio.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)

rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wishbone.CSRBank(rtio_csrs)