m-labs · Feb 23, 2016 · Feb 23, 2016
diff --git a/artiq/test/coredevice/test_analyzer.py b/artiq/test/coredevice/test_analyzer.py
@@ -12,7 +12,7 @@ def build(self):
     def run(self):
         self.ttl_inout.output()
         delay_mu(100)
-        with interleave:
+        with parallel:
             self.ttl_inout.gate_both_mu(1200)
             with sequential:
                 delay_mu(100)

diff --git a/artiq/test/coredevice/test_portability.py b/artiq/test/coredevice/test_portability.py
@@ -100,7 +100,7 @@ def build(self):
     @kernel
     def run(self):
         for i in range(3):
-            with interleave:
+            with parallel:
                 with sequential:
                     self.a.pulse(100+i, 20*us)
                     self.b.pulse(200+i, 20*us)

diff --git a/artiq/test/coredevice/test_rtio.py b/artiq/test/coredevice/test_rtio.py
@@ -16,7 +16,7 @@ def build(self):
     def run(self):
         self.ttl_inout.output()
         delay(1*us)
-        with interleave:
+        with parallel:
             # make sure not to send two commands into the same RTIO
             # channel with the same timestamp
             self.ttl_inout.gate_rising(5*us)
@@ -37,7 +37,7 @@ def build(self):
     def run(self):
         self.loop_in.input()
         delay(1*us)
-        with interleave:
+        with parallel:
             self.loop_in.gate_rising(2*us)
             with sequential:
                 delay(1*us)
@@ -57,7 +57,7 @@ def run(self):
         self.loop_clock_in.input()
         self.loop_clock_out.stop()
         delay(1*us)
-        with interleave:
+        with parallel:
             self.loop_clock_in.gate_rising(10*us)
             with sequential:
                 delay(200*ns)
@@ -110,7 +110,7 @@ def set_count(self, count):
     def run(self):
         self.ttl_inout.output()
         delay(5*us)
-        with interleave:
+        with parallel:
             self.ttl_inout.gate_rising(10*us)
             with sequential:
                 for i in range(self.npulses):

diff --git a/doc/manual/getting_started_core.rst b/doc/manual/getting_started_core.rst
@@ -156,29 +156,29 @@ The core device records the real-time IO waveforms into a circular buffer. It is
 
 Afterwards, the recorded data can be extracted and written to a VCD file using ``artiq_coreanalyzer -w rtio.vcd`` (see: :ref:`core-device-rtio-analyzer-tool`). VCD files can be viewed using third-party tools such as GtkWave.
 
-Interleave and sequential blocks
---------------------------------
+Parallel and sequential blocks
+------------------------------
 
-It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with interleave`` constructs, in which all statements execute at the same time. The execution time of the ``interleave`` block is the execution time of its longest statement.
+It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with parallel`` constructs, in which all statements execute at the same time. The execution time of the ``parallel`` block is the execution time of its longest statement.
 
 Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
 
     for i in range(1000000):
-        with interleave:
+        with parallel:
             self.ttl0.pulse(2*us)
             self.ttl1.pulse(4*us)
         delay(4*us)
 
-Within a interleave block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
+Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
 
     for i in range(1000000):
-        with interleave:
+        with parallel:
             with sequential:
                 self.ttl0.pulse(2*us)
                 delay(1*us)
                 self.ttl0.pulse(1*us)
             self.ttl1.pulse(4*us)
         delay(4*us)
 
-.. warning::
-    In its current implementation, ARTIQ only supports those pulse sequences that can be interleaved at compile time into a sequential series of on/off events. Combinations of ``interleave``/``sequential`` blocks that require multithreading (due to the parallel execution of long loops, complex algorithms, or algorithms that depend on external input) will cause the compiler to return an error.
+.. note::
+    Branches of a ``parallel`` block are executed one after another, with a reset of the internal RTIO time variable before moving to the next branch. If a branch takes a lot of CPU time, it may cause an underflow when the next branch begins its execution.
diff --git a/doc/slides/artiq_overview.tex b/doc/slides/artiq_overview.tex
@@ -117,22 +117,21 @@
   \footnotesize
   \begin{minted}[frame=leftline]{python}
 with sequential:
-    with interleave:
+    with parallel:
         a.pulse(100*MHz, 10*us)
         b.pulse(200*MHz, 20*us)
-    with interleave:
+    with parallel:
         c.pulse(300*MHz, 30*us)
         d.pulse(400*MHz, 20*us)
   \end{minted}
 
   \begin{itemize}
     \item Experiments are inherently parallel:
         simultaneous laser pulses, parallel cooling of ions in different trap zones
-    \item \verb!interleave! and \verb!sequential! contexts with arbitrary nesting
+    \item \verb!parallel! and \verb!sequential! contexts with arbitrary nesting
     \item \verb!a! and \verb!b! pulses both start at the same time
     \item \verb!c! and \verb!d! pulses both start when \verb!a! and \verb!b! are both done
       (after 20\,µs)
-    \item Implemented by inlining, loop-unrolling, and interleaving
   \end{itemize}
 \end{frame}
 
@@ -181,7 +180,7 @@
 
     @kernel
     def run(self):
-        with interleave:
+        with parallel:
           self.ion1.cool(duration=10*us)
           self.ion2.cool(frequency=...)
         self.transporter.move(speed=...)
@@ -219,11 +218,6 @@
   \frametitle{Kernel deployment to the core device}
   \footnotesize
   \begin{itemize}
-    \item RPC and exception mappings are generated
-    \item Constants and small kernels are inlined
-    \item Small loops are unrolled
-    \item Statements in interleave blocks are interleaved
-    \item Time is converted to RTIO clock cycles
     \item The Python AST is converted to LLVM IR
     \item The LLVM IR is compiled to OpenRISC machine code
     \item The OpenRISC binary is sent to the core device

diff --git a/doc/slides/taaccs.tex b/doc/slides/taaccs.tex
@@ -133,18 +133,18 @@
   \footnotesize
   \begin{minted}[frame=leftline]{python}
 with sequential:
-    with interleave:
+    with parallel:
         a.pulse(100*MHz, 10*us)
         b.pulse(200*MHz, 20*us)
-    with interleave:
+    with parallel:
         c.pulse(300*MHz, 30*us)
         d.pulse(400*MHz, 20*us)
   \end{minted}
 
   \begin{itemize}
     \item Experiments are inherently parallel:
         simultaneous laser pulses, parallel cooling of ions in different trap zones
-    \item \verb!interleave! and \verb!sequential! contexts with arbitrary nesting
+    \item \verb!parallel! and \verb!sequential! contexts with arbitrary nesting
     \item \verb!a! and \verb!b! pulses both start at the same time
     \item \verb!c! and \verb!d! pulses both start when \verb!a! and \verb!b! are both done
       (after 20\,µs)
@@ -197,7 +197,7 @@
 
     @kernel
     def run(self):
-        with interleave:
+        with parallel:
           self.ion1.cool(duration=10*us)
           self.ion2.cool(frequency=...)
         self.transporter.move(speed=...)
@@ -235,11 +235,6 @@
   \frametitle{Kernel deployment to the core device}
   \footnotesize
   \begin{itemize}
-    \item RPC and exception mappings are generated
-    \item Constants and small kernels are inlined
-    \item Small loops are unrolled
-    \item Statements in interleave blocks are interleaved
-    \item Time is converted to RTIO clock cycles
     \item The Python AST is converted to LLVM IR
     \item The LLVM IR is compiled to OpenRISC machine code
     \item The OpenRISC binary is sent to the core device