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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: dab19d23cc54
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Nov 23, 2016

  1. moninj.rs: force u32 dds_ftws

    jordens committed Nov 23, 2016
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    fbf6010 View commit details
  2. Copy the full SHA
    dab19d2 View commit details
Showing with 9 additions and 3 deletions.
  1. +7 −1 artiq/coredevice/rtio.py
  2. +2 −2 artiq/runtime.rs/src/moninj.rs
8 changes: 7 additions & 1 deletion artiq/coredevice/rtio.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,18 @@
from artiq.language.core import syscall
from artiq.language.types import TInt64, TInt32, TNone
from artiq.language.types import TInt64, TInt32, TNone, TList


@syscall(flags={"nowrite"})
def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")


@syscall(flags={"nowrite"})
def rtio_output_list(time_mu: TInt64, channel: TInt32, addr: TInt32,
data: TList(TInt32)) -> TNone:
raise NotImplementedError("syscall not simulated")


@syscall(flags={"nowrite"})
def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
raise NotImplementedError("syscall not simulated")
4 changes: 2 additions & 2 deletions artiq/runtime.rs/src/moninj.rs
Original file line number Diff line number Diff line change
@@ -18,7 +18,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {

match request {
Request::Monitor => {
let mut dds_ftws = [0; (csr::CONFIG_RTIO_DDS_COUNT as usize *
let mut dds_ftws = [0u32; (csr::CONFIG_RTIO_DDS_COUNT as usize *
csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)];
let mut reply = Reply::default();

@@ -54,7 +54,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
csr::rtio_moninj::mon_probe_sel_write(i as u8);
csr::rtio_moninj::mon_value_update_write(1);
dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
csr::rtio_moninj::mon_value_read();
csr::rtio_moninj::mon_value_read() as u32;
}
}
}