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rtio: fix DMA TimeOffset stream.connect
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sbourdeauducq committed Dec 1, 2016
1 parent d4cb1eb commit 3931d80
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/gateware/rtio/dma.py
Original file line number Diff line number Diff line change
@@ -194,8 +194,8 @@ def __init__(self):
pipe_ce = Signal()
self.sync += \
If(pipe_ce,
self.source.payload.connect(self.sink.payload,
leave_out={"timestamp"}),
self.sink.payload.connect(self.source.payload,
leave_out={"timestamp"}),
self.source.payload.timestamp.eq(self.sink.payload.timestamp
+ self.time_offset.storage),
self.source.stb.eq(self.sink.stb)

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