rtio: fix DMA TimeOffset stream.connect

sbourdeauducq · sbourdeauducq · commit 3931d8097bdd · 2016-12-01T16:43:46.000+08:00
diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
@@ -194,8 +194,8 @@ def __init__(self):
         pipe_ce = Signal()
         self.sync += \
             If(pipe_ce,
-                self.source.payload.connect(self.sink.payload,
-                                            leave_out={"timestamp"}),
+                self.sink.payload.connect(self.source.payload,
+                                          leave_out={"timestamp"}),
                 self.source.payload.timestamp.eq(self.sink.payload.timestamp
                                                  + self.time_offset.storage),
                 self.source.stb.eq(self.sink.stb)
