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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: d4cb1eb99832
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  • 4 commits
  • 5 files changed
  • 1 contributor

Commits on Dec 1, 2016

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    6c97a97 View commit details
  2. Copy the full SHA
    46dbc44 View commit details
  3. rtio: simple DMA fixes

    sbourdeauducq committed Dec 1, 2016
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    7c59688 View commit details
  4. kc705: integrate DMA

    sbourdeauducq committed Dec 1, 2016
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    d4cb1eb View commit details
Showing with 63 additions and 47 deletions.
  1. +2 −1 artiq/gateware/rtio/__init__.py
  2. +27 −24 artiq/gateware/rtio/cri.py
  3. +13 −12 artiq/gateware/rtio/dma.py
  4. +11 −5 artiq/gateware/targets/kc705.py
  5. +10 −5 artiq/gateware/targets/kc705_drtio_master.py
3 changes: 2 additions & 1 deletion artiq/gateware/rtio/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from artiq.gateware.rtio.cri import KernelInitiator, CRIDecoder
from artiq.gateware.rtio.cri import KernelInitiator, CRIInterconnectShared
from artiq.gateware.rtio.core import Channel, LogChannel, Core
from artiq.gateware.rtio.analyzer import Analyzer
from artiq.gateware.rtio.moninj import MonInj
from artiq.gateware.rtio.dma import DMA
51 changes: 27 additions & 24 deletions artiq/gateware/rtio/cri.py
Original file line number Diff line number Diff line change
@@ -160,30 +160,33 @@ def __init__(self, masters=2, slave=None):

# # #

selected = Signal(max=len(masters))

# mux master->slave signals
for name, size, direction in layout:
if direction == DIR_M_TO_S:
choices = Array(getattr(m, name) for m in masters)
self.comb += getattr(slave, name).eq(choices[selected])

# connect slave->master signals
for name, size, direction in layout:
if direction == DIR_S_TO_M:
source = getattr(slave, name)
for i, m in enumerate(masters):
dest = getattr(m, name)
if name == "arb_gnt":
self.comb += dest.eq(source & (selected == i))
else:
self.comb += dest.eq(source)

# select master
self.sync += \
If(~slave.arb_req,
[If(m.arb_req, selected.eq(i)) for i, m in enumerate(masters)]
)
if len(masters) == 1:
self.comb += masters[0].connect(slave)
else:
selected = Signal(max=len(masters))

# mux master->slave signals
for name, size, direction in layout:
if direction == DIR_M_TO_S:
choices = Array(getattr(m, name) for m in masters)
self.comb += getattr(slave, name).eq(choices[selected])

# connect slave->master signals
for name, size, direction in layout:
if direction == DIR_S_TO_M:
source = getattr(slave, name)
for i, m in enumerate(masters):
dest = getattr(m, name)
if name == "arb_gnt":
self.comb += dest.eq(source & (selected == i))
else:
self.comb += dest.eq(source)

# select master
self.sync += \
If(~slave.arb_req,
[If(m.arb_req, selected.eq(i)) for i, m in enumerate(masters)]
)


class CRIInterconnectShared(Module):
25 changes: 13 additions & 12 deletions artiq/gateware/rtio/dma.py
Original file line number Diff line number Diff line change
@@ -15,8 +15,8 @@ def __init__(self, bus=None):

aw = len(bus.adr)
dw = len(bus.dat_w)
self.sink = stream.Endpoint(["address", aw])
self.source = stream.Endpoint(["data", dw])
self.sink = stream.Endpoint([("address", aw)])
self.source = stream.Endpoint([("data", dw)])

# # #

@@ -150,16 +150,16 @@ class RecordConverter(Module):
def __init__(self, stream_slicer):
self.source = stream.Endpoint(record_layout)

hdrlen = layout_len(header_layout) - 512
hdrlen = layout_len(record_layout) - 512
record_raw = Record(record_layout)
self.comb += [
record_raw.raw_bits().eq(stream_slicer.source),

record.channel.eq(record_raw.channel),
record.timestamp.eq(record_raw.timestamp),
record.address.eq(record_raw.address),
self.source.channel.eq(record_raw.channel),
self.source.timestamp.eq(record_raw.timestamp),
self.source.address.eq(record_raw.address),
Case(record_raw.length,
{hdrlen+i*8: self.cri.o_data.eq(header.data[:])
{hdrlen+i*8: self.source.data.eq(record_raw.data[:])
for i in range(512//8)}),

self.source.stb.eq(stream_slicer.source_stb),
@@ -195,14 +195,14 @@ def __init__(self):
self.sync += \
If(pipe_ce,
self.source.payload.connect(self.sink.payload,
exclude={"timestamp"}),
leave_out={"timestamp"}),
self.source.payload.timestamp.eq(self.sink.payload.timestamp
+ self.time_offset.storage),
self.source.stb.eq(self.sink.stb)
)
self.comb += [
self.pipe_ce.eq(self.source.ack | ~self.source.stb),
self.sink.ack.eq(self.pipe_ce)
pipe_ce.eq(self.source.ack | ~self.source.stb),
self.sink.ack.eq(pipe_ce)
]


@@ -239,12 +239,12 @@ def __init__(self):
bit = i + 1
self.sync += [
If(error_set[i],
self.error_status[bit].eq(1),
self.error_status.status[bit].eq(1),
self.error_channel.status.eq(self.sink.channel),
self.error_timestamp.status.eq(self.sink.timestamp),
self.error_address.status.eq(self.sink.address)
),
If(rcsr.re, self.error_status[bit].eq(0))
If(rcsr.re, self.error_status.status[bit].eq(0))
]

self.comb += [
@@ -301,6 +301,7 @@ def __init__(self, membus):
self.submodules.slicer = RecordSlicer(len(membus.dat_w))
self.submodules.time_offset = TimeOffset()
self.submodules.cri_master = CRIMaster()
self.cri = self.cri_master.cri

self.comb += [
self.dma.source.connect(self.slicer.sink),
16 changes: 11 additions & 5 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -101,10 +101,11 @@ def __init__(self, platform, rtio_internal_clk):

class _NIST_Ions(MiniSoC, AMPSoC):
mem_map = {
"timer_kernel": 0x10000000, # (shadow @0x90000000)
"rtio": 0x20000000, # (shadow @0xa0000000)
"i2c": 0x30000000, # (shadow @0xb0000000)
"mailbox": 0x70000000 # (shadow @0xf0000000)
"timer_kernel": 0x10000000,
"rtio": 0x20000000,
"rtio_dma": 0x30000000,
"i2c": 0x50000000,
"mailbox": 0x70000000
}
mem_map.update(MiniSoC.mem_map)

@@ -143,8 +144,13 @@ def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.submodules.rtio = rtio.KernelInitiator(self.rtio_core.cri)
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")

15 changes: 10 additions & 5 deletions artiq/gateware/targets/kc705_drtio_master.py
Original file line number Diff line number Diff line change
@@ -17,9 +17,10 @@

class Master(MiniSoC, AMPSoC):
mem_map = {
"timer_kernel": 0x10000000, # (shadow @0x90000000)
"rtio": 0x20000000, # (shadow @0xa0000000)
"mailbox": 0x70000000 # (shadow @0xf0000000)
"timer_kernel": 0x10000000,
"rtio": 0x20000000,
"rtio_dma": 0x30000000,
"mailbox": 0x70000000
}
mem_map.update(MiniSoC.mem_map)

@@ -56,9 +57,13 @@ def __init__(self, **kwargs):
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_core = rtio.Core(rtio_channels, 3)

self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
self.submodules.rtio = rtio.KernelInitiator(self.cridec.master)
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.drtio.cri, self.rtio_core.cri])


def main():